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參數(shù)資料
| 型號： | ISL6563CRZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Two-Phase Multi-Phase Buck PWM Controller with Integrated MOSFET Drivers |
| 中文描述： | SWITCHING CONTROLLER, 255 kHz SWITCHING FREQ-MAX, PQCC24 |
| 封裝： | 4 X 4 MM, ROHS COMPLIANT, PLASTIC, MO-220-VGGD-2, QFN-24 |
| 文件頁數(shù)： | 6/19頁 |
| 文件大?。?/td> | 516K |
| 代理商： | ISL6563CRZ |
6
FN9126.6
April 13, 2005
settings. These pins are internally pulled high, to
approximately 1.2V, by 40
μ
A (typically) internal current
sources; the internal pull-up current decrease to 0 as the VID
voltage approaches the internal pull-up voltage. All VID pins
are compatible with external pull-up voltages not exceeding
the IC’s bias voltage.
DACSEL/VID5 (Pin 3)
If VRM10 pin is grounded, DACSEL/VID5 represents the 6th
voltage identification input from the VRM10-compliant
microprocessor, otherwise known as VID5. If VRM10 pin is
open or pulled high, DACSEL/VID5 selects the compliance
standard for the internal DAC: pulled to ground it encodes the
DAC with AMD Hammer VID codes, while left open or pulled
high, it encodes the DAC with Intel VRM9.0 codes.
VRM10 (Pin 4)
This pin selects VRM10.0 DAC compliance when grounded.
Left open, it allows selection of either VRM9.0 or Hammer
DAC compliance via DACSEL pin.
ENLL (Pin 21)
This pin is a precision-threshold (approximately 0.6V) enable
pin. Held low, this pin disables controller operation. Pulled
high, the pin enables the controller for operation.
FB and COMP (Pins 6, 5)
The internal error amplifier’s inverting input and output
respectively. These pins are connected to the external
network used to compensate the regulator’s feedback loop.
An internal current source injects the average current
sampled through R
ISEN
into the FB pin. Pulling COMP to
ground through an impedance lower than 15
disables the
controller (same effect as ENLL pulled low).
ISEN (Pin 7)
This pin is used to close the current-feedback loop and set
the overcurrent protection threshold. A resistor connected
between this pin and VCC has a voltage drop forced across
it equal to that sampled across the lower MOSFET’s r
DS(ON)
during approximately the middle of its conduction interval.
The resulting current through this resistor is used for channel
current balancing, overcurrent protection and is sourced to
the FB pin for load-line regulation. The voltage across the
R
ISEN
resistor is time multiplexed between the two
channels.
Use the following equation to select the proper R
ISEN
resistor:
r
I
50
μ
A
where:
r
DS(ON)
= lower MOSFET drain-source ON resistance (
)
I
OUT
= channel maximum output current (A)
Read ‘Current Feedback’ paragraph for more information.
UGATE1, 2 (Pins 19, 12)
Connect these pins to the upper MOSFETs’ gates. These
pins are used to control the upper MOSFETs and are
monitored for shoot-through prevention purposes. Maximum
individual channel duty cycle is limited to 66%.
BOOT1, 2 (Pins 20, 11)
These pins provide the bias voltage for the upper MOSFETs’
drives. Connect these pins to appropriately-chosen external
bootstrap capacitors. Internal bootstrap diodes connected to
the PVCC pins provide the necessary bootstrap charge.
PHASE1, 2 (Pins 18, 13)
Connect these pins to the sources of the upper MOSFETs.
These pins are the return path for the upper MOSFETs’
drives.
LGATE1, 2 (Pins 17, 15)
These pins are used to control the lower MOSFETs and are
monitored for shoot-through prevention purposes. Connect
these pins to the lower MOSFETs’ gates.
OFS (Pin 9)
This pin is used to create an adjustable output voltage offset.
For no offset, leave this pin open. For negative offset, connect
an R’
OFS
resistor from this pin to VCC and size it according to
the following equation:
where:
V
OFFSET
= desired output voltage offset magnitude (mV)
For positive output voltage offset, connect an R
OFS
resistor
from this pin to GND, sizing it according to the following
equation:
For more information, refer to the ‘Output Voltage Offset
Programming’ paragraph.
SSEND (Pin 10)
This pin is an end of Soft-Start (SS) indicator; open drain
output device stays ON during soft-start, and goes open when
soft-start ends.
R
ISEN
------------------------------------------
=
R
′
OFS
R
1
V
OFFSET
--------------------------
×
=
R
OFS
R
1
OFFSET
--------------------------
×
=
ISL6563
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| ISL6563CRZ-T | 功能描述:電流型 PWM 控制器 P6 TWO PHS CONT INTEGRTD DRVRS DESKT RoHS:否 制造商:Texas Instruments 開關(guān)頻率:27 KHz 上升時間: 下降時間: 工作電源電壓:6 V to 15 V 工作電源電流:1.5 mA 輸出端數(shù)量:1 最大工作溫度:+ 105 C 安裝風格:SMD/SMT 封裝 / 箱體:TSSOP-14 |
| ISL6563CRZ-TK | 功能描述:IC CTRLR PWM MULTIPHASE 24-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 標準包裝:43 系列:- 應(yīng)用:控制器，Intel VR11 輸入電壓:5 V ~ 12 V 輸出數(shù):1 輸出電壓:0.5 V ~ 1.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-QFN（7x7） 包裝:管件 |
| ISL6563EVAL1 | 制造商:Intersil Corporation 功能描述:DEV TOOLS, EVAL BD - Bulk 制造商:Intersil 功能描述:ISL6563 EVALRD |
| ISL6563IR | 功能描述:電流型 PWM 控制器 2-PH RoHS:否 制造商:Texas Instruments 開關(guān)頻率:27 KHz 上升時間: 下降時間: 工作電源電壓:6 V to 15 V 工作電源電流:1.5 mA 輸出端數(shù)量:1 最大工作溫度:+ 105 C 安裝風格:SMD/SMT 封裝 / 箱體:TSSOP-14 |
| ISL6563IR-T | 功能描述:IC CTRLR PWM MULTIPHASE 24-QFN RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,000 系列:- 應(yīng)用:電源，ICERA E400，E450 輸入電壓:4.1 V ~ 5.5 V 輸出數(shù):10 輸出電壓:可編程 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:42-WFBGA，WLCSP 供應(yīng)商設(shè)備封裝:42-WLP 包裝:帶卷 (TR) |
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