
13
FN9098.5
May 12, 2005
INDUCTOR DCR Sensing
An inductor has a distributed direct current winding
resistance (DCR). Consider the inductor DCR as a separate
lumped quantity as shown in Figure 4. The channel current,
I
L
, flowing through the inductor, also passes through the
DCR. Equation 4 shows the s-domain equivalent voltage,
V
L
, across the inductor.
A simple R-C network across the inductor extracts the DCR
voltage, as shown in Figure 5.
The voltage on the capacitor, V
C
, can be shown to be
proportional to the channel current I
L
(see Equation 5).
+
If the R-C network components are selected such that the R-
C time constant matches the inductor L/DCR time constant,
then V
C
is equal to the voltage drop across the DCR.
The capacitor voltage, V
C
, is replicated across the sense
resistor R
ISEN
. so that the current flowing through the sense
resistor is proportional to the inductor current. Equation 6
shows that the relationship between the channel current and
the sensed current I
SEN
, is driven by the value of the sense
resistor and the inductor DCR.
ISEN
Current Sampling
During the forced off-time following a PWM transition low, the
associated channel current sense amplifier reproduces a
signal , I
SEN
, proportional to the inductor current, I
L
.
Regardless of the current sense method, I
SEN
is simply a
scaled version of the inductor current. Coincident with the
falling edge of the PWM signal, the sample and hold circuitry
samples I
SEN
. This is illustrated in Figure 5. The sample
time, t
SAMP
, is fixed and equal to 1/3 of the switching period,
t
SW
. Therefore, the sample current, I
n
, is proportional to the
output current and held for one switching cycle. The sample
current is used for current balance, load-line regulation, and
overcurrent protection.
Channel-Current Balance
The sampled currents I
n
, from each active channel are
summed together and divided by the number of active
channels. The resulting cycle average current, I
AVG
,
provides a measure of the total load current demand on the
converter during each switching cycle. Channel current
balance is achieved by comparing the sampled current of
each channel to the cycle average current, and making an
appropriate adjustment to each channel pulse width based
on the error. Intersil’s patented current-balance method is
illustrated in Figure 6, with error correction for channel 1
represented. In the figure, the cycle average current
combines with the channel 1 sample, I
1
, to create an error
signal I
ER
. The filtered error signal modifies the pulse width
commanded by V
COMP
to correct any unbalance and force
I
ER
toward zero. The same method for error signal correction
is applied to each active channel.
V
L
I
L
s L
DCR
+
(
)
=
(EQ. 4)
V
C
s
-------------
1
+
DCR I
L
(
)
--------------------------------------------------------------------
=
(EQ. 5)
FIGURE 4. DCR SENSING CONFIGURATION
I
n
ISEN
IL
RISEN
=
-
+
ISEN-
SAMPLE
&
HOLD
ISL6561 INTERNAL CIRCUIT
V
IN
ISEN+
PWM(n)
ISL6561
R
ISEN
DCR
L
INDUCTOR
R
V
OUT
C
OUT
-
+V
C
(s)
C
I
L
s
( )
-
+
V
L
I
SEN
I
L
-----------------
=
(EQ. 6)
t
SAMP
t
----------
SW
-----------------
=
=
(EQ. 7)
FIGURE 5. SAMPLE AND HOLD TIMING
TIME
PWM
I
L
SWITCHING PERIOD
I
SEN
SAMPLE CURRENT, I
n
t
SAMP
ISL6561