參數(shù)資料
型號(hào): ISL6552CRZ
廠商: INTERSIL CORP
元件分類: 穩(wěn)壓器
英文描述: Microprocessor CORE Voltage Regulator Multi-Phase Buck PWM Controller
中文描述: SWITCHING CONTROLLER, 1500 kHz SWITCHING FREQ-MAX, PQCC20
封裝: 5 X 5 MM, PLASTIC, MO-220VHHC, QFN-20
文件頁(yè)數(shù): 12/18頁(yè)
文件大?。?/td> 421K
代理商: ISL6552CRZ
12
Current Sensing and Balancing
Overview
The ISL6552 samples the on-state voltage drop across each
synchronous rectifier FET, Q2, as an indication of the
inductor current in that phase, see Figure 7. Neglecting AC
effects (to be discussed later), the voltage drop across Q2 is
simply r
DS(ON)
(Q2) x
inductor current (I
L
). Note that I
L
, the
inductor current, is either 1/2, 1/3, or 1/4 of the total current
(I
LT
), depending on how many phases are in use.
The voltage at Q2’s drain, the PHASE node, is applied to the
R
ISEN
resistor to develop the I
ISEN
current to the ISL6552
ISEN pin. This pin is held at virtual ground, so the current
through R
ISEN
is I
L
x
r
DS(ON)
(Q2)/R
ISEN
.
The I
ISEN
current provides information to perform the
following functions:
1. Detection of an over-current condition
2. Reduce the regulator output voltage with increasing load
current (droop)
3. Balance the I
L
currents in multiple channels
Over-Current, Selecting R
ISEN
The current detected through the R
ISEN
resistor is
averaged with the current(s) detected in the other 1, 2, or 3
channels. The averaged current is compared with a
trimmed,
internally generated current, and used to detect
an over-current condition.
The nominal current through the R
ISEN
resistor should be
50
μ
A at full output load current, and the nominal trip point for
over-current detection is 165% of that value, or 82.5
μ
A.
Therefore, R
ISEN
= I
L
x r
DS(ON)
(Q2)/50
μ
A.
For a full load of 25A per phase, and an r
DS(ON)
(Q2) of
4m
, R
ISEN
= 2k
.
The over-current trip point would be 165% of 25A, or ~41A
per phase. The R
ISEN
value can be adjusted to change the
over-current trip point, but it is suggested to stay within
±
25%
of nominal.
Droop, Selection of R
IN
The average of the currents detected through the R
ISEN
resistors is also steered to the FB pin. There is no DC return
path connected to the FB pin except for R
IN
, so the average
current creates a voltage drop across R
IN
. This drop
increases the apparent V
CORE
voltage with increasing load
current, causing the system to decrease V
CORE
to maintain
balance at the FB pin. This is the desired “droop” voltage used
to maintain V
CORE
within limits under transient conditions.
With a high dv/dt load transient, typical of high performance
microprocessors, the largest deviations in output voltage occur
at the leading and trailing edges of the load transient. In order to
fully utilize the output-voltage tolerance range, the output
voltage is positioned in the upper half of the range when the
output is unloaded and in the lower half of the range when the
FIGURE 7. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM SHOWING CURRENT AND VOLTAGE SAMPLING
CURRENT
SENSING
COMPARATOR
PWM
CIRCUIT
AVERAGING
CURRENT
SENSING
FROM
OTHER
CHANNELS
SAWTOOTH
GENERATOR
+
DIFFERENCE
R
ISEN
+
CORRECTION
ERROR
AMPLIFIER
FB
COMP
REFERENCE
DAC
TO OTHER
CHANNELS
ISEN
R
IN
R
FB
C
c
V
CORE
Q1
Q2
COMPARATOR
REFERENCE
TO OVER
CURRENT
TRIP
L
01
PHASE
INDUCTOR
CURRENT(S)
FROM
OTHER
CHANNELS
PWM
I
L
ISL6552
C
O
R
L
V
IN
ONLY ONE OUTPUT
STAGE SHOWN
HIP6601
-
-
+
+
-
+
ISL6552
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