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參數(shù)資料
| 型號： | ISL6551IR |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Wide-Range Power-Supply Controller 8-SO -20 to 85 |
| 中文描述： | DUAL SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PQCC28 |
| 封裝： | 6 X 6 MM, PLASTIC, MO-220VJJC, QFN-28 |
| 文件頁數(shù)： | 13/26頁 |
| 文件大小： | 619K |
| 代理商： | ISL6551IR |
13
FN9066.4
July 8, 2005
Leading Edge Blanking (R_LEB)
- In current mode control, the sensed switch (FET) current is
processed in the Ramp Adjust and LEB circuits and then
compared to a control signal (EAO voltage). Spikes, due to
parasitic elements in the bridge circuit, would falsely trigger
the comparator generating the PWM signal. To prevent
false triggering, the leading edge of the sensed current
signal is blanked out by a period that can be programmed
with the R_LEB resistor. Internal switches gate the analog
input to the PWM comparator, implementing the blanking
function that eliminates response degrading delays which
would be caused if filtering of the current feedback was
incorporated. The current ramp is blanked out during the
resonant delay period because no switching occurs in the
lower FETs. The leading edge blanking function will not be
activated until the soft-start (CSS) reaches over 400mV, as
illustrated in Figures 4 and 9. The leading edge blanking
(LEB) function can be disabled by tying the R_LEB pin to
VDD, i.e., LEB=1. Never leave the pin floating.
- The blanking time can be estimated with Equation 9,
whose relationship can be seen in Figure 8. The
percentages in the figure are the tolerances at the two
endpoints of the curve.
t
R
500
450
400
350
300
250
200
150
100
50
0
20
40
60
80
100
120
+37%
+4%
-24%
+18%
FIGURE 7. R_RESDLY vs RESDLY
R_RESDLY (k
)
(EQ. 9)
t
LEB
= 2 x R_LEB / k
+ 15 (ns)
FIGURE 8. R_LEB vs t
LEB
+20%
-18%
+51%
-11%
300
250
200
150
100
50
0
20
40
60
80
100
120
140
t
L
R_LEB (k
)
ADD RAMP
399K
BGREF
VDD
BLANK
0.1
μ
R_RA
R_RA
ISENSE
200mV
+
-
RESDLY
LEB
SSL
ADJ_RAMP
RAMP_OUT
(TO PWM
COMPARATOR)
200mV
0
RAMP_OUT
200mV
ADJ_RAMP
ISENSE
RESDLY
LEB
SSL
RAMP_OUT
0
X
X
BLANK
X
0
0
BLANK
1
1
X
NO BLANK
1
X
1
NO BLANK
FIGURE 9. SIMPLIFIED RAMP ADJUST AND LEADING EDGE BLANKING CIRCUITS
(See Fig. 4)
SET
BLANKING
TIME
R_LEB
R_LEB
ISL6551
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