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參數(shù)資料
| 型號(hào)： | ISL6540IRZA |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Single-Phase Buck PWM Controller with Integrated High Speed MOSFET Driver and Pre-Biased Load Capability |
| 中文描述： | SWITCHING CONTROLLER, 2000 kHz SWITCHING FREQ-MAX, PQCC28 |
| 封裝： | 5 X 5 MM, ROHS COMPLIANT, PLASTIC, MO-220VHHD-1, QFN-28 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大小： | 518K |
| 代理商： | ISL6540IRZA |
11
FN9214.0
March 9, 2006
Functional Description
Initialization
The ISL6540 automatically initializes upon receipt of power
without requiring any special sequencing of the input
supplies. The Power-On Reset (POR) function continually
monitors the input supply voltages (PVCC,VFF, VCC) and
the voltage at the EN pin. Assuming the EN pin is pulled to
above ~0.49V, the POR function initiates soft-start operation
after all input supplies exceed their POR thresholds.
With all input supplies above their POR thresholds, driving
the EN pin above 0.49 V initiates a soft-start cycle. In
addition to normal TTL logic, the enable pin can be used as
a voltage monitor with programmable hysteresis through the
use of the internal 10
μ
A sink current and an external resistor
divider. This feature is especially designed for applications
that have input rails greater than a 3.3V and require a
specific input rail POR and Hysteresis levels for better
undervoltage protection. Consider for a 12V application
choosing R
UP
= 100k
and R
DOWN
= 5.76k
there by
setting the rising threshold (V
EN_RTH
) to 10V and the falling
threshold (V
EN_FTH
) to 9V, for 1V of hysteresis (V
EN_HYS
).
Care should be taken to prevent the voltage at the EN pin
from exceeding VCC when using the programmable UVLO
functionality.
Soft-start
The POR function activates the internal 38
μ
A OTA which
begins charging the external capacitor (C
SS
) on the SS pin to a
target voltage of VCC. The ISL6540’s soft-start logic continues
to charge the SS pin until the voltage on COMP exceeds the
bottom of the oscillator ramp, at which point, the driver outputs
are enabled, with the low side MOSFET first being held low for
200ns to provide for charging of the bootstrap capacitor. Once
the driver outputs are enabled, the OTA’s target voltage is then
changed to the margined (if margining is being used) reference
voltage (V
REF_MARG
), and the SS pin is ramped up or down
accordingly. This method reduces startup surge currents due to
a pre-charged output by inhibiting regulator switching until the
control loop enters its linear region. By ramping the positive
input of the error amplifier to VCC and then to V
REF_MARG
, it is
even possible to mitigate surge currents from outputs that are
pre-charged above the set output voltage. As the SS pin
connects directly to the non-inverting input of the Error
Amplifier, noise on this pin should be kept to a minimum
through careful routing and part placement.
To prevent noise
injection into the error amplifier the SS capacitor should be
located within 150mils of the SS and GND pins.
Soft-start is
declared done when the drivers have been enabled and the SS
pin is within ±3mV of V
REF_MARG
.
Power Good
The power good comparator references the voltage on the
soft-start pin to prevent accidental tripping during margining.
The trip points are shown on Figure 3. Additionally, power
good will not be asserted until after the completion of the soft-
start cycle. A 0.1
μ
F capacitor at the PG_DLY pin will add an
additional ~5ms delay to the assertion of power good.
PG_DLY does not delay the deassertion of power good.
VMON
Under and Overvoltage Protection
The Undervoltage (UV) and Overvoltage (OV) protection
circuitry compares the voltage on the VMON pin with the
VCC POR
VFF POR
PVCC POR
EN POR
SOFT-START
HIGH = ABOVE POR; LOW = BELOW POR
AND
FIGURE 1. SOFT-START INITIALIZATION LOGIC
V
REF
I
EN_HYS
=10
μ
A
R
UP
R
DOWN
VIN
R
UP
V
EN_HYS
-------------------------
=
R
DOWN
R
V
EN_REF
EN_FTH
---------------------------–
=
V
EN_FTH
V
EN_RTH
V
EN_HYS
–
=
Sys_Enable
FIGURE 2. ENABLE POR CIRCUIT
FIGURE 3. UNDERVOLTAGE-OVERVOLTAGE WINDOW
-15%
-9%
V
REF_MARG
+9%
+15%
UV
UV
OV
GOOD
GOOD
T
PG_DLY
C
PG_DLY
A
--------------
=
ISL6540
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|---|---|
| ISL6540IRZA-T | 制造商:Intersil Corporation 功能描述:VOLT MODE PWM CNTRLR 0.6V TO 20V 30A 28QFN EP - Tape and Reel 制造商:Intersil 功能描述:W/ANNEAL 3 3V-20V INPUT SYNC PWM CONT |
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| ISL65426EVAL1Z | 功能描述:EVAL BOARD 1 FOR ISL65426 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - DC/DC 與 AC/DC（離線）SMPS 系列:* 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:DC/DC，步降 輸出及類型:1，非隔離 功率 - 輸出:- 輸出電壓:3.3V 電流 - 輸出:3A 輸入電壓:4.5 V ~ 28 V 穩(wěn)壓器拓?fù)浣Y(jié)構(gòu):降壓 頻率 - 開關(guān):250kHz 板類型:完全填充 已供物品:板 已用 IC / 零件:L7981 其它名稱:497-12113STEVAL-ISA094V1-ND |
| ISL65426EVAL3Z | 制造商:Intersil Corporation 功能描述: |
| ISL65426HRZ | 功能描述:IC REG BUCK SYNC ADJ 6A DL 50QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 開關(guān)穩(wěn)壓器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:降壓（降壓） 輸出類型:兩者兼有 輸出數(shù):1 輸出電壓:5V，1 V ~ 10 V 輸入電壓:3.5 V ~ 28 V PWM 型:電流模式 頻率 - 開關(guān):220kHz ~ 1MHz 電流 - 輸出:600mA 同步整流器:無 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:16-SSOP（0.154"，3.90mm 寬） 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:16-QSOP |
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