參數(shù)資料
型號(hào)： ISL6540CRZA
廠(chǎng)商： INTERSIL CORP
元件分類(lèi)： 穩(wěn)壓器
英文描述： Single-Phase Buck PWM Controller with Integrated High Speed MOSFET Driver and Pre-Biased Load Capability
中文描述： SWITCHING CONTROLLER, 2000 kHz SWITCHING FREQ-MAX, PQCC28
封裝： 5 X 5 MM, ROHS COMPLIANT, PLASTIC, MO-220VHHD-1, QFN-28
文件頁(yè)數(shù)： 16/20頁(yè)
文件大小： 518K
代理商： ISL6540CRZA
16
FN9214.0
March 9, 2006
Figure 8 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS pin and locate the capacitor, C
SS
close to the SS pin (as described earlier) as the internal
current source is only 38
μ
A. Provide local decoupling
between PVCC and PGND pins as described earlier. Locate
the capacitor, C
BOOT
as close as practical to the BOOT and
PHASE pins.
Compensating the Converter
The ISL6540 single-phase converter is a voltage-mode
controller. This section highlights the design considerations for
a voltage-mode controller requiring external compensation. To
address a broad range of applications, a type-3 feedback
network is recommended (see Figure 9).
Figure 10 highlights the voltage-mode control loop for a
synchronous-rectified buck converter, when using an internal
differential remote sense amplifier. The output voltage
(V
OUT
) is regulated to the reference voltage, VREF, level.
The error amplifier output (COMP pin voltage) is compared
with the oscillator (OSC) triangle wave to provide a pulse-
width modulated wave with an amplitude of V
IN
at the
PHASE node. The PWM wave is smoothed by the output
filter (L and C). The output filter capacitor bank’s equivalent
series resistance is represented by the series resistor ESR.
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
COMP
. This function is dominated by a
DC gain, given by d
MAX
V
IN
/V
OSC
, and shaped by the
output filter, with a double pole break frequency at F
LC
and a
zero at F
CE
. For the purpose of this analysis C and ESR
represent the total output capacitance and its equivalent
series resistance.
The compensation network consists of the error amplifier
(internal to the ISL6540) and the external R
1
-R
3
, C
1
-C
3
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F
0
; typically 0.1 to 0.3 of F
SW
) and adequate
phase margin (better than 45°). Phase margin is the
difference between the closed loop phase at F
0dB
and 180°.
The equations that follow relate the compensation network’s
poles, zeros and gain to the components (R
1
, R
2
, R
3
, C
1
, C
2
,
and C
3
) in Figures 9 and 10. Use the following guidelines for
locating the poles and zeros of the compensation network:
1. Select a value for R
1
(1k
to 10k
, typically). Calculate
value for R
2
for desired converter bandwidth (F
0
). If
setting the output voltage to be equal to the reference set
voltage as shown in Figure 22, the design procedure can
be followed as presented. However, when setting the
output voltage via a resistor divider placed at the input of
the differential amplifier (as shown in Figure 10), in order
to compensate for the attenuation introduced by the
resistor divider, the below obtained R
2
value needs be
multiplied by a factor of (R
OS
+R
FB
)/R
OS
. The remainder
of the calculations remain unchanged, as long as the
compensated R
2
value is used.
FIGURE 9. COMPENSATION CONFIGURATION FOR ISL6540
WHEN USING DIFFERENTIAL REMOTE SENSE
ISL6540
COMP
C
1
R
2
R
1
FB
VMON
C
2
R
3
C
3
F
LC
2
π
L C
---------------------------
=
F
CE
---------------------------------
=
FIGURE 10. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
-
+
E/A
VREF
COMP
C
1
R
2
R
1
FB
C
2
R
3
C
3
L
C
V
IN
PWM
CIRCUIT
HALF-BRIDGE
DRIVE
OSCILLATOR
ESR
EXTERNAL CIRCUIT
ISL6540
V
OUT
V
OSC
DCR
UGATE
PHASE
LGATE
-
+
VMON
VSEN+
VSEN-
C
SEN
R
OS
R
FB
ISL6540
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