參數(shù)資料
型號(hào)： ISL6539
廠商： Intersil Corporation
英文描述： Wide Input Range Dual PWM Controller with DDR Option
中文描述： 寬輸入范圍雙PWM控制器的DDR選項(xiàng)
文件頁(yè)數(shù)： 11/20頁(yè)
文件大小： 503K
代理商： ISL6539
11
FN9144.4
June 6, 2005
The small signal transfer function from the error amplifier
output voltage V
c
to the output voltage V
o
can be written in
the following expression:
The dc gain is derived by shorting the inductor and opening
the capacitor. There is one zero and two poles in this transfer
function.
The zero is related to ESR and the output capacitor.
The first pole is a low frequency pole associated with the
output capacitor and its charging resistors. The inductor can
be regarded as short. The second pole is the high frequency
pole related to the inductor. At high frequency the output cap
can be regarded as a short circuit. By approximation, the
poles and zero are inversely proportional to the time
constants, associated with inductor and capacitor, by the
following expressions:
Since the current loop separates the LC resonant poles into
two distant poles, and ESR zero tends to cancel the high
frequency pole, the second order system behaves like a first
order system. This control method simplifies the design of
the internal compensator and makes it possible to
accommodate many applications having a wide range of
parameters. The schematics for the internal compensator is
shown in Figure 6.
Its transfer function can be written as the following:
where
f
z1
= 6.98kHz, f
z2
= 380kHz, and f
p1
= 137kHz
Outside the ISL6539 chip, a capacitor C
z
can be placed in
parallel with the top resistor in the feedback resistor divider,
as shown in Figure 4. In this case the transfer function from
the output voltage to the middle point of the divider can be
written as:
The ratio of R
1
and R
2
is determined by the output voltage
set point; therefore, the position of the pole and zero
frequency in the above equation may not be far apart;
however, they can improve the loop gain and phase margin
with the proper design.
The Cz can bring the high frequency transient output voltage
variation directly to the VSEN pin to cause the PGOOD drop.
Such an effect should be considered in the selection of Cz.
From the analysis above, the system loop gain can be
written as:
Figure 7 shows the composition of the system loop gain. As
shown in the graph, the power stage became a well damped
second order system compared to the LC filter
characteristics. The ESR zero is so close to the high
frequency pole that they cancel each other out. The power
stage behaves like a first order system. With an internal
compensator, the loop gain transfer function has a cross
TABLE 1. PWM COMPARATOR RAMP AMPLITUDE FOR
DUAL SWITCHER APPLICATION
VIN PIN CONNECTIONS
VRAMP
AMPLITUDE
Ch1 and Ch2
Input Voltage Input voltage >4.2V
Vin/8
Input voltage <4.2V
1.25V
GND
1.25V
TABLE 2. PWM COMPARATOR RAMP VOLTAGE AMPLITUDE
FOR DDR APPLICATION
VIN PIN CONNECTION
VRAMP
AMPLITUDE
Ch1
Input Voltage
Input voltage >4.2V
Vin/8
Input voltage <4.2V
1.25V
GND
1.25V
Ch2
Input voltage >4.2V
0.625V
GND
1.25V
G s
G
m
R
R
i
DCR
R
o
+
+
---------------------------------------
--------
1
+
------------
1
+
------------
1
+
---------------------------------------------------------
=
Wz
ESR*C
o
-----------------------
=
Wp1
DCR
ESR
R
i
+
R
o
+
(
*C
o
------------------------------------------------------------------------------
=
Wp2
R
------+
DCR
ESR
L
o
+
R
o
||
=
FIGURE 6. THE INTERNAL COMPENSATOR
+
1.25pF
1M 16.7pF
500K
300K
VSEN
0.9V
TO PWM
COMPARATOR
4.4K
Vc
ISEN
Gcomp s
( )
1.857
--------------------------------------------------------------------------------------------
10
5
--------------
1
+
--------------
1
+
s
2
f
p1
---------------
1
+
=
Gfd s
R
R
1
R
2
---------+
sR
C
1
1
+
2
z
1
+
---------------------------------------------
=
Gloop s
( )
G s
Gcomp s
Gfd
=
s
( )
ISL6539
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