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參數(shù)資料
| 型號(hào)： | ISL6531EVAL1 |
| 廠(chǎng)商： | Intersil Corporation |
| 英文描述： | Dual 5V Synchronous Buck Pulse-Width Modulator (PWM) Controller for DDRAM Memory VDDQ and VTT Termination |
| 中文描述： | 雙同步降壓5V的脈寬調(diào)制（PWM）控制器，用于數(shù)據(jù)存儲(chǔ)器內(nèi)存VDDQ和VTT終端 |
| 文件頁(yè)數(shù)： | 6/17頁(yè) |
| 文件大?。?/td> | 461K |
| 代理商： | ISL6531EVAL1 |
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6
Functional Pin Description
24 LEAD (SOIC)
TOP VIEW
32 LEAD 5X5 (QFN)
TOP VIEW
BOOT1 and BOOT2
These pins provide bias voltage to the upper MOSFET
drivers. A single capacitor bootstrap circuit may be used to
create a BOOT voltage suitable to drive a standard N-
Channel MOSFET.
UGATE1 and UGATE2
Connect UGATE1 and UGATE2 to the corresponding upper
MOSFET gate. These pins provide the gate drive for the
upper MOSFETs. UGATE2 is also monitored by the adaptive
shoot through protection to determine when the upper FET
of the V
TT
regulator has turned off.
LGATE1 and LGATE2
Connect LGATE1 and LGATE2 to the corresponding lower
MOSFET gate. These pins provide the gate drive for the
lower MOSFETs. These pins are monitored by the adaptive
shoot through protection circuitry to determine when the
lower FET has turned off.
PGND1 and PGND2
These are the power ground connections for the gate drivers
of the PWM controllers. Tie these pins to the ground plane
through the lowest impedence connection available.
OCSET/SD
A resistor (R
OCSET
) connected from this pin to the drain of
the upper MOSFET of the V
DDQ
regulator sets the
overcurrent trip point. R
OCSET
, an internal 40
μ
A current
source (I
OCS
), and the upper MOSFET on-resistance
(r
DS(ON)
) set the V
DDQ
converter overcurrent (OC) trip point
according to the following equation:
An overcurrent trip cycles the soft-start function.
Pulling the OCSET/SD pin to ground resets the ISL6531 and
all external MOSFETS are turned off allowing the two output
voltage power rails to float.
PGOOD
A high level on this open-drain output indicates that both the
V
DDQ
and V
TT
regulators are within normal operating
voltage ranges.
GNDA
Signal ground for the IC. Tie this pin to the ground plane
through the lowest impedence connection available.
VCC
The 5V bias supply for the chip is connected to this pin. This
pin is also the positive supply for the lower gate driver,
LGATE2. Connect a well decoupled 5V supply to this pin.
V2_SD
A high level on the V2_SD input places the V
TT
controller
into “sleep” mode. In sleep mode, both UGATE2 and
LGATE2 are driven low, effectively floating the V
TT
supply.
15
16
17
10
9
8
VREF_IN
PHASE2
SENSE2
N/C
VCC
GNDA
18
19
20
21
22
23
24
7
6
5
4
3
2
1
BOOT1
PHASE1
FB1
SENSE1
VREF
PGND1
PVCC1
OCSET/SD
V2_SD
PGOOD
N/C
LGATE1
COMP1
UGATE1
13
14
12
11
UGATE2
LGATE2
PGND2
BOOT2
B
B
U
U
P
P
L
P
P
B
B
U
P
P
L
V
PHASE 1
VREF
FB1
COMP1
SENSE1
VREF_IN
GNDA
GNDA
PVCC1
OCSET/SD
V2_SD
PGOOD
N/C
SENSE2
N/C
VCC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
9
10
11
12
13
14
15
16
I
PEAK
I
-------------------------------------------
R
DS ON
)
=
ISL6531
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