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參數(shù)資料
| 型號： | ISL6531CR |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Dual 5V Synchronous Buck Pulse-Width Modulator (PWM) Controller for DDRAM Memory VDDQ and VTT Termination |
| 中文描述： | DUAL SWITCHING CONTROLLER, 325 kHz SWITCHING FREQ-MAX, PQCC32 |
| 封裝： | 5 X 5 MM, PLASTIC, MO-220-VHHD-2, MLFP-32 |
| 文件頁數(shù)： | 8/17頁 |
| 文件大?。?/td> | 461K |
| 代理商： | ISL6531CR |
8
Shoot-Through Protection
A shoot-through condition occurs when both the upper
MOSFET and lower MOSFET are turned on simultaneously,
effectively shorting the input voltage to ground. To protect
the regulators from a shoot-through condition, the ISL6531
incorporates specialized circuitry which insures that
complementary MOSFETs are not ON simultaneously.
The adaptive shoot-through protection utilized by the V
DDQ
regulator looks at the lower gate drive pin, LGATE1, and the
phase node, PHASE1, to determine whether a MOSFET is
ON or OFF. If PHASE1 is below 0.8V, the upper gate is
defined as being OFF. Similarly, if LGATE1 is below 0.8V, the
lower MOSFET is defined as being OFF. This method of
shoot-through protection allows the V
DDQ
regulator to
source current only.
Due to the necessity of sinking current, the V
TT
regulator
employs a modified protection scheme from that of the
V
DDQ
regulator. If the voltage from UGATE2 or from
LGATE2 to GND is less than 0.8V, then the respective
MOSFET is defined as being OFF and the other MOSFET is
turned ON.
Since the voltage of the lower MOSFET gates and the upper
MOSFET gate of the V
TT
supply are being measured to
determine the state of the MOSFET, the designer is
encouraged to consider the repercussions of introducing
external components between the gate drivers and their
respective MOSFET gates before actually implementing
such measures. Doing so may interfere with the shoot-
through protection.
Power Down Mode
DDRAM systems include a sleep state in which the V
DDQ
voltage to the memories is maintained, but signaling is
suspended. During this mode the V
TT
termination voltage is
no longer needed. The only load placed on the V
TT
bus is
the leakage of the associated signal pins of the DDRAM and
memory controller ICs.
When the V2_SD input of the ISL6531 is driven high, the
V
TT
regulator is placed into a “sleep” state. In the sleep state
the main V
TT
regulator is disabled, with both the upper and
lower MOSFETs being turned off. The V
TT
bus is maintained
at close to
via a low current window regulator
which drives V
TT
via the SENSE2 pin. Maintaining V
TT
at
consumes negligible power and enables rapid
wake-up from sleep mode without the need of softstarting
the V
TT
regulator. During this power down mode, PGOOD is
held LOW.
Output Voltage Selection
The output voltage of the V
DDQ
regulator can be
programmed to any level between V
IN
(i.e. +5V) and the
internal reference, 0.8V. An external resistor divider is used
to scale the output voltage relative to the reference voltage
and feed it back to the inverting input of the error amplifier,
see Figure 3.F However, since the value of R1 affects the
values of the rest of the compensation components, it is
advisable to keep its value less than 5k
. R4 can be
calculated based on the following equation:
OUT1
If the output voltage desired is 0.8V, simply route V
DDQ
back
to the FB pin through R1, but do not populate R4.
V
TT
Reference Overdrive
The ISL6531 allows the designer to bypass the internal 50%
tracking of V
DDQ
that is used as the reference for V
TT
. The
ISL6531 was designed to divide down the V
DDQ
voltage by
50% through two internal matched resistances. These
resistances are typically 200k
.
FIGURE 2. SOFT-START INTERVAL
0V
TIME
VCC (5V)
(1V/DIV
)
T1
T2
T0
V
DDQ
(2.5V)
V
TT
(1.25V)
1
2
--
V
DDQ
1
2
--
V
DDQ
R4
–
-------------------------------------
=
FIGURE 3. OUTPUT VOLTAGE SELECTION OF V
DDQ
+
R1
C3
C
OUT1
+5V
V
DDQ
R4
L
OUT1
ISL6531
C4
Q1
FB1
UGATE1
VCC
BOOT1
COMP1
D1
R2
C2
C1
R3
PHASE1
LGATE1
Q2
ISL6531
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