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參數(shù)資料
| 型號(hào)： | ISL6530CBZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Dual 5V Synchronous Buck Pulse-Width Modulator (PWM) Controller for DDRAM Memory VDDQ and VTT Termination |
| 中文描述： | DUAL SWITCHING CONTROLLER, 325 kHz SWITCHING FREQ-MAX, PDSO24 |
| 封裝： | LEAD FREE, PLASTIC, MS-013-AD, SOIC-24 |
| 文件頁數(shù)： | 11/17頁 |
| 文件大?。?/td> | 540K |
| 代理商： | ISL6530CBZ |
11
FN9052.2
November 15, 2004
nodes. Use copper filled polygons on the top and bottom
circuit layers for the phase nodes. Use the remaining printed
circuit layers for small signal wiring. The wiring traces from
the GATE pins to the MOSFET gates should be kept short
and wide enough to easily handle the 1A of drive current.
The switching components should be placed close to the
ISL6530 first. Minimize the length of the connections
between the input capacitors, C
IN
, and the power switches
by placing them nearby. Position both the ceramic and bulk
input capacitors as close to the upper MOSFET drain as
possible. Position the output inductor and output capacitors
between the upper MOSFET and lower diode and the load.
The critical small signal components include any bypass
capacitors, feedback components, and compensation
components. Position the bypass capacitor, C
BP
, close to the
VCC pin with a via directly to the ground plane. Place the
PWM converter compensation components close to the FB
and COMP pins. The feedback resistors for both regulators
should also be located as close as possible to the relevant
FB pin with vias tied straight to the ground plane as required.
Feedback Compensation
Figure 8 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
OUT
) is regulated to the Reference voltage level. The
error amplifier (Error Amp) output (V
E/A
) is compared with
the oscillator (OSC) triangular wave to provide a pulse-
width modulated (PWM) wave with an amplitude of V
IN
at
the PHASE node. The PWM wave is smoothed by the output
filter (L
O
and C
O
).
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
E/A
. This function is dominated by a DC
Gain and the output filter (L
O
and C
O
), with a double pole
break frequency at F
LC
and a zero at F
ESR
. The DC Gain of
the modulator is simply the input voltage (V
IN
) divided by the
peak-to-peak oscillator voltage
V
OSC
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6530) and the impedance networks Z
IN
and Z
FB
. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f
0dB
) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f
0dB
and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R
1
, R
2
,
R
3
, C
1
, C
2
, and C
3
) in Figure 7. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick gain (R
2
/R
1
) for desired converter bandwidth.
2. Place first zero below filter’s double pole (~75% F
LC
).
3. Place second zero at filter’s double pole.
4. Place first pole at the ESR zero.
5. Place second pole at half the switching frequency.
6. Check gain against error amplifier’s open-loop gain.
7. Estimate phase margin - repeat if necessary.
V
DDQ
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
L
OUT1
C
OUT1
C
IN
+5V V
IN
KEY
COMP1
ISL6530
UGATE1
R4
R
2A
C
BP
FB1
GND
VCC
FIGURE 7. PRINTED CIRCUIT BOARD POWER PLANES
AND ISLANDS
R
1A
BOOT1
C
2A
VIA CONNECTION TO GROUND PLANE
L
Q1
C
BOOT1
PHASE1
D1
R
3A
C
3A
C
1A
Q2
LGATE1
PHASE1
V
TT
L
OUT2
C
OUT2
UGATE2
L
Q3
C
BOOT2
PHASE2
Q4
LGATE2
PHASE2
+5V V
IN
BOOT2
D2
V
DDQ
SENSE1
PGND1
PGND2
COMP1
R
2B
FB1
R
1B
C
2B
R
3B
C
3B
C
1B
SENSE2
F
LC
2
π
x L
O
x C
O
-----------------------------------------
=
F
ESR
O
------------------------------------------
=
ISL6530
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