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參數(shù)資料
| 型號： | ISL6529EVAL1 |
| 廠商： | Intersil Corporation |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Dual Regulator.Synchronous Rectified Buck PWM and Linear Power Controller |
| 中文描述： | 雙Regulator.Synchronous整流降壓PWM和線性功率控制器 |
| 文件頁數(shù)： | 12/19頁 |
| 文件大小： | 623K |
| 代理商： | ISL6529EVAL1 |
12
FN9070.5
April 12, 2005
The Compensation Network
To provide for system stability with a low ESR output
capacitor, where pole cancellation by the capacitor is outside
the frequencies of interest, a phase lead network must be
used to compensate for the phase lag resulting from
MOSFET output resistance and the output capacitor.
Figure 11 shows the type II compensation network
configuration and a simplified straight line representation of
the network response. By using the equations in Figure 11,
the values of R12 and C4 can be adjusted to the frequency
where phase lead begins. The second equation shows the
upper frequency where phase advance is complete. After
capacitor C4 becomes effectively an ac short, the mid band
gain is set by the R12/R5 ratio as shown on Figure 11.
Several simulations illustrate the compensation with the
more difficult 5m
, 100
μ
F output capacitor. Figure 10
previously showed the Bode plots where the phase
response comes dangerously near the oscillatory 180° state
at unity gain. A type II network applied across the error
amplifier inverting input to the output can be configured to
perform this function.
Figure 12 shows the Bode plot of only the compensation
network with the system to illustrate the phase boost in the
system. Essentially the phase lead region must be moved to
advance the phase where it is close to an oscillatory state.
Increasing the value of C4 moves the response lower, aiding
the lagging phase at low frequencies and low load current.
This operation will reduce phase compensation at higher
80
60
40
20
0
0
-50
-150
-100
-200
10
1K
100
10K
100K
1M
10M
G
P
FREQUENCY (Hz)
BODE PLOT OF REGULATOR (N0 COMP) AT 3 OUTPUT CURRENTS
3A
3A
55mA
1mA
55mA
1mA
55mA
1mA
FIGURE 10. LOOP RESPONSE WITH ONLY 100μF, 5m
OUTPUT CAPACITOR
10
10
20
30
0
40
0
50
60
70
100
1,000
10,000
10K
100,000
100K
1,000,000
10,000,000
60
40
20
80
-90
-45
P
G
-135
FREQUENCY (Hz)
----------------------------------
20
R12
--R5
log
2
π
R12
C16 C4
-------------------------
C4
+
----------------------------1
R5
C4
INTERNAL 0.8V
REFERENCE
-
+
REGULATED
OUTPUT
R12
C16
FB
TO MOSFET
DRIVE 2
ISL6529
FIGURE 11. SCHEMATIC AND BODE PLOT OF
COMPENSATION NETWORK
80
60
40
20
0
0
-50
-150
-100
-200
G
P
10
1K
100
10K
100K
1M
10M
FREQUENCY (Hz)
BODE PLOT OF REGULATOR (COMP ONLY) AT 3 OUTPUT CURRENTS
3A
3A
1mA
54mA
1mA
COMPENSATION:
C16 = 10pF
C4 = 470pF
R16 = 200K
FIGURE 12. LOOP RESPONSE WITH COMPENSATION
NETWORK ONLY
135°
80
60
40
20
0
0
-50
-150
-100
-200
G
P
10
1K
100
10K
100K
1M
10M
FREQUENCY (Hz)
BODE PLOT OF COMPENSATED REGULATOR AT 3 OUTPUT CURRENTS
3A
54mA
3A
1mA
54mA
3A
1mA
1mA
COMPENSATION:
C16 = 10pF
C4 = 470pF
R16 = 200K
FIGURE 13. INVERTING INPUT TO OUTPUT GAIN AND
PHASE WITH COMPENSATION AND 100μF, 5m
OUTPUT CAPACITOR
ISL6529, ISL6529A
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