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參數(shù)資料
| 型號： | ISL6523 |
| 廠商： | Intersil Corporation |
| 英文描述： | Adjustable Precision Shunt Regulator 3-SOT-23 0 to 70 |
| 中文描述： | VRM8.5雙雙PWM和線性電源系統(tǒng)控制器 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 498K |
| 代理商： | ISL6523 |
11
Figure 10 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
OUT
) is regulated to the Reference voltage level. The
reference voltage level is the DAC output voltage (DACOUT) for
PWM1. The error amplifier output (V
E/A
) is compared with the
oscillator (OSC) triangular wave to provide a pulse-width
modulated wave with an amplitude of V
IN
at the PHASE node.
The PWM wave is smoothed by the output filter (L
O
and C
O
)..
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
E/A
. This function is dominated by a DC
Gain, given by V
IN
/V
OSC
, and shaped by the output filter, with
a double pole break frequency at F
LC
and a zero at F
ESR
.
Modulator Break Frequency Equations
2
π
L
O
The compensation network consists of the error amplifier
(internal to the ISL6523) and the impedance networks Z
IN
and
Z
FB
. The goal of the compensation network is to provide a
closed loop transfer function with high 0dB crossing frequency
(f
0dB
) and adequate phase margin. Phase margin is the
difference between the closed loop phase at f
0dB
and 180
o
.
The equations below relate the compensation network’s poles,
zeros and gain to the components (R1, R2, R3, C1, C2, and
C3) in Figure 10. Use these guidelines for locating the poles
and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
ST
Zero Below Filter’s Double Pole (~75% F
LC
)
3. Place 2
ND
Zero at Filter’s Double Pole
4. Place 1
ST
Pole at the ESR Zero
5. Place 2
ND
Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Compensation Break Frequency Equations
Figure 11 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown in Figure 11. Using the above guidelines
should yield a Compensation Gain similar to the curve plotted.
The open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at F
P2
with the capabilities
of the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 11 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the compensation
transfer function and plotting the gain.
The compensation gain uses external impedance networks
Z
FB
and Z
IN
to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than
45 degrees. Include worst case component variations when
determining phase margin.
PWM2 Controller Feedback Compensation
To reduce the number of external small-signal components
required by a typical application, the standard PWM
controller is internally stabilized. The only stability criteria
that needs to be met relates the minimum value of the output
FIGURE 10. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
V
OUT
OSC
REFERENCE
L
O
C
O
ESR
V
IN
V
OSC
ERROR
AMP
PWM
COMP
DRIVER
(PARASITIC)
Z
FB
+
-
DACOUT
R
1
R
3
R
2
C
3
C
2
C
1
COMP
V
OUT
FB
Z
FB
ISL6523
Z
IN
DRIVER
DETAILED COMPENSATION COMPONENTS
PHASE
V
E/A
+
-
+
-
Z
IN
F
LC
C
O
×
×
---------------------------------------
=
F
ESR
O
-----------------------------------------
=
F
Z1
-----------------------------------
=
F
Z2
R3
)
C3
×
------------------------+
=
F
P1
2
π
R
2
+
----------------------
×
×
------------------------------------------------------
=
F
P2
-----------------------------------
=
100
80
60
40
20
0
-20
-40
-60
F
P1
F
Z2
10M
1M
100K
10K
1K
100
10
OPEN LOOP
ERROR AMP GAIN
F
Z1
F
P2
F
LC
F
ESR
COMPENSATION
GAIN
G
FREQUENCY (Hz)
MODULATOR
GAIN
FIGURE 11. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
CLOSED LOOP
GAIN
20
P
–
-----------------
log
20
-------
log
ISL6523
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| ISL6523CB | 功能描述:IC CTRLR VRM8.5 PWM DUAL 28-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,000 系列:- 應用:電源，ICERA E400，E450 輸入電壓:4.1 V ~ 5.5 V 輸出數(shù):10 輸出電壓:可編程 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:42-WFBGA，WLCSP 供應商設(shè)備封裝:42-WLP 包裝:帶卷 (TR) |
| ISL6523CB-T | 功能描述:IC CTRLR VRM8.5 PWM DUAL 28-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,000 系列:- 應用:電源，ICERA E400，E450 輸入電壓:4.1 V ~ 5.5 V 輸出數(shù):10 輸出電壓:可編程 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:42-WFBGA，WLCSP 供應商設(shè)備封裝:42-WLP 包裝:帶卷 (TR) |
| ISL6523CBZ | 功能描述:IC CTRLR VRM8.5 PWM DUAL 28-SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 標準包裝:43 系列:- 應用:控制器，Intel VR11 輸入電壓:5 V ~ 12 V 輸出數(shù):1 輸出電壓:0.5 V ~ 1.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-VFQFN 裸露焊盤 供應商設(shè)備封裝:48-QFN（7x7） 包裝:管件 |
| ISL6523CBZ-T | 功能描述:IC CTRLR VRM8.5 PWM DUAL 28-SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 標準包裝:43 系列:- 應用:控制器，Intel VR11 輸入電壓:5 V ~ 12 V 輸出數(shù):1 輸出電壓:0.5 V ~ 1.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-VFQFN 裸露焊盤 供應商設(shè)備封裝:48-QFN（7x7） 包裝:管件 |
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