
13
Layout Considerations
The typical application employing an ISL6505 is a fairly 
straight forward implementation. Like with any other linear 
regulator, attention has to be paid to the few potentially 
sensitive small signal components, such as those connected 
to sensitive nodes or those supplying critical bypass current.
The power components (pass transistors) and the 
controller IC should be placed first. The controller should 
be placed in a central position on the motherboard, closer 
to the memory controller chip and processor, but not 
excessively far from the 3.3V
DUAL
 island or the I/O 
circuitry. Ensure the 1V2VID, 3V3, and 3V3DL connections 
are properly sized to carry 100mA without exhibiting 
significant resistive losses at the load end. Similarly, the 
input bias supply (5V
SB
) can carry a significant level of 
current - for best results, ensure it is connected to its 
respective source through an adequately sized trace. The 
pass transistors should be placed on pads capable of 
heatsinking matching the device’s power dissipation. 
Where applicable, multiple via connections to a large 
internal plane can significantly lower localized device 
temperature rise.
Placement of the decoupling and bulk capacitors should 
follow a placement reflecting their purpose. As such, the high-
frequency decoupling capacitors should be placed as close as 
possible to the load they are decoupling; the ones decoupling 
the controller close to the controller pins, the ones decoupling 
the load close to the load connector or the load itself (if 
embedded). Even though bulk capacitance (aluminum 
electrolytics or tantalum capacitors) placement is not as 
critical as the high-frequency capacitor placement, having 
these capacitors close to the load they serve is preferable.
The critical small signal components include the soft-start 
capacitor, C
SS
, as well as all the high-frequency decoupling 
capacitors. Locate these components close to the respective 
pins of the control IC, and connect them to ground through a 
via placed close to the ground pad. Minimize any leakage 
current paths from the SS node, as the internal current 
source is only 10μA (typical).
A multi-layer printed circuit board is recommended. 
Figure 12 shows the connections to most of the components 
in the circuit. Note that the individual capacitors shown each 
could represent numerous physical capacitors. Dedicate one 
solid layer for a ground plane and make all critical 
component ground connections through vias placed as close 
to the component terminal as possible. Dedicate another 
solid layer as a power plane and break this plane into 
smaller islands of common voltage levels. Ideally, the power 
plane should support both the input power and output power 
nodes. Use copper filled polygons on the top and bottom 
circuit layers to create power islands connecting the filtering 
components (output capacitors) and the loads. Use the 
remaining printed circuit layers for small signal wiring.
Component Selection Guidelines
The output capacitors should be selected to allow the output 
voltage to meet the dynamic regulation requirements of 
active state operation (S0, S1). The load transient for the 
various microprocessor system’s components may require 
high quality capacitors to supply the high slew rate (di/dt) 
current demands. Thus, it is recommended that the output 
capacitors be selected for transient load regulation, paying 
attention to their parasitic components (ESR, ESL).
Also, during the transition between active and sleep states 
on the 3.3V
DUAL
/3.3V
SB
 and 5V
DUAL
 outputs, there is a 
short interval of time during which none of the power pass 
elements are conducting - during this time the output 
capacitors have to supply all the output current. The output 
voltage drop during this brief period of time can be easily 
approximated with the following formula:
×
=
, where
V
OUT
 - output voltage drop
ESR
OUT
 - output capacitor bank ESR
I
OUT
 - output current during transition
C
OUT
 - output capacitor bank capacitance
t
t
 - active-to-sleep or sleep-to-active transition time (10
μ
s typ.)
L
V
OUT1
C
HF1
L
FIGURE 12. PRINTED CIRCUIT BOARD ISLANDS
V
OUT3
Q2
Q3
Q4
CSS
+12V
IN
+5V
SB
CIN
VIA CONNECTION TO GROUND PLANE
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT/POWER PLANE LAYER
ISL6505
DR1
V
OUT4
SS
GND
5VDLSB
3V3DLSB
KEY
5VSB
DLA
Q5
C
BULK4
L
C5VSB
L
C
HF3
C
HF4
5VDL
+5V
IN
+3.3V
IN
3V3DL
3V3
C
BULK2
C
HF2
C
BULK1
1V2VID
C
BULK3
V
OUT2
5V
FB1
Q6
V
OUT
I
OUT
ESR
OUT
t
OUT
---------------
+
ISL6505