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參數(shù)資料
| 型號(hào)： | ISL6441 |
| 廠商： | Intersil Corporation |
| 英文描述： | 1.4MHz Dual, Out-of-Phase, Step-Down PWM and Single Linear Controller(1.4MHz兩路,異相，降壓型PWM，外加一路線性控制器) |
| 中文描述： | 1.4MHz的雙通道，外的階段，降壓型PWM和線性控制器單（1.4MHz的兩路，異相，降壓型脈寬調(diào)制，外加一路線性控制器） |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 380K |
| 代理商： | ISL6441 |
11
FN9197.1
October 4, 2005
For example, a single large FET with 15nC total gate charge
requires 15nC X 1.4MHz = 21mA. Also, at higher input
voltages with larger FETs, the power dissipation across the
internal 5V will increase. Excessive dissipation across this
regulator must be avoided to prevent junction temperature
rise. Larger FETs can be used with 5V ±10% input
applications. The thermal overload protection circuit will be
triggered if the VCC_5V output is short circuited. Connect
VCC_5V to VIN for 5V ±10% input applications.
Soft-Start Operation
When soft-start is initiated, the voltage on the SS pin of the
enabled PWM channels starts to ramp gradually, due to the
5
μ
A current sourced into the external capacitor. The output
voltage follows the soft-start voltage.
When the SS pin voltage reaches 0.8V, the output voltage of
the enabled PWM channel reaches the regulation point, and
the soft-start pin voltage continues to rise. At this point the
PGOOD and fault circuitry is enabled. This completes the
soft-start sequence. Any further rise of SS pin voltage does
not affect the output voltage. By varying the values of the
soft-start capacitors, it is possible to provide sequencing of the
main outputs at start-up. The soft-start time can be obtained
from the following equation:
The soft-start capacitors can be chosen to provide startup
tracking for the two PWM outputs. This can be achieved by
choosing the soft-start capacitors such that the soft-start
capacitor ration equals the respective PWM output voltage
ratio. For example, if I use PWM1 = 1.2V and PWM2 = 3.3V
then the soft-start capacitor ration should be,
C
SS1
/C
SS1
= 1.2/3.3 = 0.364. Figure 14 shows that soft-start
waveform with C
SS1
= 0.01μF and C
SS2
= 0.027μF.
Output Voltage Programming
A resistive divider from the output to ground sets the output
voltage of either PWM channel. The center point of the
divider shall be connected to FBx pin. The output voltage
value is determined by the following equation.
where R1 is the top resistor of the feedback divider network
and R2 is the resistor connected from FBx to ground.
Out-of-Phase Operation
The two PWM controllers in the ISL6441 operate 180
o
out-
of-phase to reduce input ripple current. This reduces the
input capacitor ripple current requirements, reduces power
supply-induced noise, and improves EMI. This effectively
helps to lower component cost, save board space and
reduce EMI.
Dual PWMs typically operate in-phase and turn on both
upper FETs at the same time. The input capacitor must then
support the instantaneous current requirements of both
controllers simultaneously, resulting in increased ripple
voltage and current. The higher RMS ripple current lowers
the efficiency due to the power loss associated with the ESR
of the input capacitor. This typically requires more low-ESR
capacitors in parallel to minimize the input voltage ripple and
ESR-related losses, or to meet the required ripple current
rating.
With dual synchronized out-of-phase operation, the high-
side MOSFETs of the ISL6441 turn on 180
o
out-of-phase.
The instantaneous input current peaks of both regulators no
longer overlap, resulting in reduced RMS ripple current and
input voltage ripple. This reduces the required input
capacitor ripple current rating, allowing fewer or less
expensive capacitors, and reducing the shielding
requirements for EMI. The typical operating curves show the
synchronized 180° out-of-phase operation.
T
SOFT
0.8V
C
A
-----------
=
FIGURE 13. SOFT-START OPERATION
VCC_5V
1V/DIV
SS1
1V/DIV
V
OUT1
1V/DIV
FIGURE 14. PWM1 AND PWM2 OUTPUT TRACKING DURING
STARTUP
V
OUT1
1V/DIV
V
OUT2
1V/DIV
V
OUTx
0.8VR1
R2
+
R2
=
ISL6441
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