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參數(shù)資料
| 型號： | ISL6440A |
| 廠商： | Intersil Corporation |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Advanced PWM and Triple Linear Power Controller for Gateway Applications |
| 中文描述： | 先進的PWM和三線性電源控制器，用于網(wǎng)關(guān)應用 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 749K |
| 代理商： | ISL6440A |
9
for the linear controllers is that they monitor the VSEN pins
for undervoltage events. Should excessive currents cause
the voltage at the VSEN pins to fall below the linear
undervoltage threshold, the LUV signal sets the
overcurrent latch if C
SS
is
fully charged. Blanking the LUV
signal during the C
SS
charge interval allows the linear
outputs to build above the undervoltage threshold during
normal operation. Cycling the bias input power off then on
resets the counter and the fault latch.
A resistor (R
OCSET
) programs the overcurrent trip level for
the PWM converter. As shown in Figure 5, the internal
200
μ
A current sink, I
OCSET
develops a voltage across
R
OCSET
(V
SET
) that is referenced to V
IN
. The DRIVE
signal enables the overcurrent comparator (OVER-
CURRENT). When the voltage across the upper MOSFET
(V
DS
) exceeds V
SET
, the overcurrent comparator trips to
set the overcurrent latch. Both V
SET
and V
DS
are
referenced to V
IN
and a small capacitor across R
OCSET
helps V
OCSET
track the variations of V
IN
due to MOSFET
switching. The overcurrent function will trip at a peak
inductor current (I
PEAK)
determined by:
I
DS ON
)
The OC trip point varies with MOSFET’s r
DS(ON)
temperature variations. To avoid overcurrent tripping in the
normal operating load range, determine the R
OCSET
resistor from the equation above with:
1. The maximum r
DS(ON)
at the highest junction temperature.
2. The minimum I
OCSET
from the specification table.
3. Determine I
PEAK
for I
PEAK
> I
OUT(MAX)
+ (
I)/2, where
I is the output inductor ripple current.
For an equation for the ripple current see the section under
component guidelines titled
PWM Output Inductor Selection
.
OUT1 Voltage Program
The output voltage of the PWM converter is programmed to
discrete levels between 1.3V
DC
and 3.5V
DC
. This output
(OUT1) is designed to supply the core voltage of Intel’s
advanced microprocessors. The voltage identification (VID)
pins program an internal voltage reference (DACOUT) with a
TTL-compatible 5-bit digital-to-analog converter. The level of
DACOUT also sets the PGOOD and OVP thresholds.
Table 1 specifies the DACOUT voltage for the different
combinations of connections on the VID pins. The VID pins
can be left open for a logic 1 input, because they are
internally pulled up to an internal voltage of about 5V by a
10
μ
A current source. Changing the VID inputs during
operation is not recommended and could toggle the PGOOD
signal and exercise the overvoltage protection.
S
0A
0V
2V
4V
FIGURE 4. OVERCURRENT OPERATION
TIME
T1
T2
T3
T0
T4
F
0V
10V
OVERLOAD
APPLIED
FAULT
REPORTED
COUNT
= 1
COUNT
= 2
COUNT
= 3
I
PEAK
=
R
×
---------------------------------------------------
UGATE
OCSET
PHASE
OVER-
CURRENT
+
-
GATE
CONTROL
VCC
OC
200
μ
A
V
DS
i
D
V
SET
R
OCSET
V
IN
= +5V
OVERCURRENT TRIP:
VDS
I
OCSET
+
+
FIGURE 5. OVERCURRENT DETECTION
PWM
DRIVE
iD
rDS ON
)
×
IOCSET
ROCSET
×
>
VSET
>
VPHASE
VOCSET
VIN
VIN
VDS
VSET
–
=
–
=
ISL6440A
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