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參數(shù)資料
| 型號： | ISL6425 |
| 廠商： | Intersil Corporation |
| 英文描述： | Quadruple 2-Input Positive-AND Gates 14-TSSOP -40 to 85 |
| 中文描述： | 單輸出LNB電源和控制穩(wěn)壓器，帶有I2C接口的先進(jìn)衛(wèi)星機(jī)頂盒設(shè)計 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大小： | 285K |
| 代理商： | ISL6425 |
10
FN9176.1
February 8, 2005
Received Data (
I
2
C
Bus Read Mode)
The ISL6425 can provide to the master a copy of the System
Register information via the I
2
C bus in read mode. The read
mode is Master activated by sending the chip address with
R/W bit set to 1. At the following Master generated clock bits,
the ISL6425 issues a byte on the SDA data bus line (MSB
transmitted first).
At the ninth clock bit the MCU master can:
Acknowledge the reception, starting in this way the
transmission of another byte from the ISL6425.
Not acknowledge, stopping the read mode
communication.
While the whole register is read back by the microprocessor,
only the two read-only bits, OLF and OTF, convey diagnostic
information about the ISL6425.
Power-On I
2
C Interface Reset
The I
2
C interface built into the ISL6425 is automatically reset
at power-on. The I
2
C interface block will receive a Power OK
logic signal from the UVLO circuit. This signal will go HIGH
when chip power is OK. As long as this signal is LOW, the
interface will not respond to any I
2
C commands and the
system register SR is initialized to all zeros, thus keeping the
power blocks disabled.
TABLE 5. SYSTEM REGISTER (SR1 AND SR2) CONFIGURATION
SR1
DCL
ISEL1
ENT1
LLC1
VSEL1
EN1
OLF1
FUNCTION
0
X
X
X
0
0
X
X
SR1 is selected
0
X
X
X
0
0
1
X
Vout1 = 13V, Vboost1 = 13V + Vdrop
0
X
X
X
0
1
1
X
Vout1 = 18V, Vboost1 = 18V + Vdrop
0
X
X
X
1
0
1
X
Vout1 = 14V, Vboost1 = 14V + Vdrop
0
X
X
X
1
1
1
X
Vout1 = 19V, Vboost1 = 19V + Vdrop
0
X
X
0
X
X
1
X
22kHz tone is controlled by the DSQIN pin
0
X
X
1
X
X
1
X
22kHz tone is ON, the DSQIN input is disabled
0
X
0
X
X
X
1
X
Iout1 = 425mA max.
0
X
1
X
X
X
1
X
Iout1 = 775mA max.
0
1
X
X
X
X
1
X
Dynamic current limit NOT selected
0
0
X
X
X
X
1
X
Dynamic current limit selected
0
X
X
X
X
X
0
X
PWM and Linear for channel 1 disabled
SR2
-
-
-
-
EN2
OTF
-
FUNCTION
1
X
X
X
X
0
X
X
SR2 is selected; to read OTF flag.
NOTE: OTF is a “Read Only” bit and X indicates a “Don’t Care” condition for the function specified.
TABLE 6. READING SYSTEM REGISTERS
DCL ISEL ENT LLC VSEL EN OTF OLF
FUNCTION
These bits are read as they were
after the last write operation.
0
Tj
≤
130°C, Normal
operation
1
Tj > 150°C, Power
blocks disabled
0
Iout < Imax, Normal
operation
1
Iout > Imax, Overload
protection triggered
ISL6425
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