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參數(shù)資料
| 型號： | ISL6421ERZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | CABLE ASSEMBLY; BNC MALE TO UHF MALE; 52 OHM, RG8A/U COAX; 12" CABLE LENGTH |
| 中文描述： | 0.95 A SWITCHING CONTROLLER, 240 kHz SWITCHING FREQ-MAX, PQCC32 |
| 封裝： | 5 X 5 MM, LEAD FREE, PLASTIC, MO-220VHHD-2, QFN-32 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 261K |
| 代理商： | ISL6421ERZ |
8
Byte Format
Every byte put on the SDA line must be 8-bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an acknowledge
bit. Data is transferred with the most significant bit first (MSB).
Acknowledge
The master (microprocessor) puts a resistive HIGH level on
the SDA line during the acknowledge clock pulse (Figure 3).
The peripheral that acknowledges has to pull down (LOW)
the SDA line during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse. (Of course,
set-up and hold times must also be taken into account.)
The peripheral which has been addressed has to generate
an acknowledge after the reception of each byte, otherwise
the SDA line remains at the HIGH level during the ninth
clock pulse time. In this case, the master transmitter can
generate the STOP information in order to abort the transfer.
The ISL6421 will not generate the acknowledge if the
POWER OK signal from the UVLO is LOW.
Transmission Without Acknowledge
Avoiding detection of the acknowledgement, the
microprocessor can use a simpler transmission; it waits one
clock without checking the slave acknowledging, and sends
the new data.
This approach, though, is less protected from error and
decreases the noise immunity.
ISL6421 Software Description
Interface Protocol
The interface protocol is comprised of the following, as
shown below in Table 2:
A start condition (S)
A chip address byte (MSB on left; the LSB bit determines
read (1) or write (0) transmission) (the assigned I
2
C slave
address for the ISL6421 is 0001 00XX)
A sequence of data (1 byte + Acknowledge)
A stop condition (P)
Transmitted Data (
I
2
C
bus WRITE mode)
When the R/W bit in the chip is set to 0, the main
microprocessor can write on the system register (SR1) of the
ISL6421 via I
2
C bus. These will be written by the
microprocessor as shown below.
SDA
SCL
FIGURE 3. ACKNOWLEDGE ON THE I
2
C BUS
1
2
8
9
ACKNOWLEDGE
FROM SLAVE
MSB
START
TABLE 2. INTERFACE PROTOCOL
S
0
0
0
1
0
0
0
R/W
ACK Data (8 bits) ACK
P
TABLE 3. SYSTEM REGISTER 1 (SR1)
R, W
R, W
R, W
R, W
R, W
R, W
R, W
R
SR1
DCL
X
ENT1
LLC1
VSEL1
EN1
OLF1
TABLE 4. SYSTEM REGISTER 2 (SR2)
R, W
R, W
R, W
R, W
R, W
R, W
R
R
SR2
X
X
X
X
EN2
OTF
X
System Register Format
R, W = Read and Write bit
R = Read-only bit
All bits reset to 0 at Power-On
TABLE 5. SYSTEM REGISTER (SR1 AND SR2) CONFIGURATION
SR
DCL
ISEL1
ENT1
LLC1
VSEL1
EN1
OLF1
FUNCTION
0
1
0
0
1
SR1 is selected
0
1
0
0
1
Vout1 = 13V, Vboost1 = 13V + Vdrop
0
1
0
1
1
Vout1 = 18V, Vboost1 = 18V + Vdrop
0
1
1
0
1
Vout1 = 14V, Vboost1 = 14V + Vdrop
0
1
1
1
1
Vout1 = 19V, Vboost1 = 19V + Vdrop
0
1
0
1
22kHz tone is controlled by the DSQIN pin
0
1
1
1
22kHz tone is ON, the DSQIN input is disabled
ISL6421
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| ISL6422BERZ-T | 功能描述:直流/直流開關(guān)轉(zhuǎn)換器 DL LNB SUPPLY + CONT VAGEG W/I2C RoHS:否 制造商:STMicroelectronics 最大輸入電壓:4.5 V 開關(guān)頻率:1.5 MHz 輸出電壓:4.6 V 輸出電流:250 mA 輸出端數(shù)量:2 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT |
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