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參數資料
| 型號： | ISL6420AIRZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Advanced Single Synchronous Buck Pulse-Width Modulation (PWM) Controller |
| 中文描述： | 0.05 A SWITCHING CONTROLLER, 1400 kHz SWITCHING FREQ-MAX, PQCC20 |
| 封裝： | 4 X 4 MM, GREEN, PLASTIC, MO-220, QFN-20 |
| 文件頁數： | 16/20頁 |
| 文件大小： | 560K |
| 代理商： | ISL6420AIRZ |
16
FN9169.1
October 13, 2005
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6420A) and the impedance networks Z
IN
and Z
FB
. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f
0dB
) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f
0dB
and
180°. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 16. Use these guidelines for
locating the poles and zeros of the compensation network:
Compensation Break Frequency Equations
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
ST
Zero Below Filter’s Double Pole
(~75% F
LC
)
3. Place 2
ND
Zero at Filter’s Double Pole
4. Place 1
ST
Pole at the ESR Zero
5. Place 2
ND
Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Figure 17
shows an asymptotic plot of the DC/DC
converter’s gain vs. frequency. The actual Modulator Gain
has a high gain peak due to the high Q factor of the output
filter and is not shown in Figure 17. Using the above
guidelines should give a Compensation Gain similar to the
curve plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F
P2
with the capabilities of the error amplifier. The Closed Loop
Gain is constructed on the log-log graph of Figure 17 by
adding the Modulator Gain (in dB) to the Compensation Gain
(in dB). This is equivalent to multiplying the modulator
transfer function to the compensation transfer function and
plotting the gain.
The compensation gain uses external impedance networks
Z
FB
and Z
IN
to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin.
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (effective series resistance) and voltage rating
requirements rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements. For example, Intel
recommends that the high frequency decoupling for the
Pentium Pro be composed of at least forty (40) 1.0μF
ceramic capacitors in the 1206 surface-mount package.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors.
The bulk capacitor’s ESR will determine the output ripple
voltage and the initial voltage drop after a high slew-rate
transient. An aluminum electrolytic capacitor's ESR value is
related to the case size with lower ESR available in larger
F
LC
L
O
2
π
C
O
--------------------------------------
=
(EQ. 4)
F
ESR
O
)
--------------------------------------------
=
(EQ. 5)
F
Z1
2
π
R
2
C1
----------------------------------
=
(EQ. 6)
F
P1
2
π
R2
--------+
------------------------------------------------------
=
(EQ. 7)
F
Z2
+
2
π
R1
R3
(
)
C3
-----------------------------------------------------
=
(EQ. 8)
F
P2
=
----------------------------------
(EQ. 9)
100
80
60
40
20
0
-20
-40
-60
F
P1
F
Z2
10M
1M
100K
10K
1K
100
10
OPEN LOOP
ERROR AMP GAIN
F
Z1
F
P2
F
LC
F
ESR
COMPENSATION
GAIN
G
FREQUENCY (Hz)
20LOG
(V
IN
/
V
OSC
)
MODULATOR
GAIN
20LOG
(R2/R1)
CLOSED LOOP
GAIN
FIGURE 17. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
ISL6420A
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ISL6420AIRZS2698 | 制造商:Intersil Corporation 功能描述:PB-FREE W/ANNEAL SYNC BUCK PWM CONT. WITH 4.5V-28V INPUT,20L - Rail/Tube |
| ISL6420AIRZ-TK | 功能描述:IC REG CTRLR BUCK PWM VM 20-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標準包裝:75 系列:- PWM 型:電流模式 輸出數:1 頻率 - 最大:1MHz 占空比:81% 電源電壓:4.3 V ~ 13.5 V 降壓:是 升壓:是 回掃:是 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:0°C ~ 70°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:管件 產品目錄頁面:1051 (CN2011-ZH PDF) 其它名稱:296-2543-5 |
| ISL6420AIRZ-TKR5264 | 功能描述:IC REG CTRLR BUCK PWM VM 20-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- PWM 型:電流模式 輸出數:1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR) |
| ISL6420AIRZ-TKS2698 | 制造商:Intersil Corporation 功能描述:PB-FREE W/ANNEAL SYNC BUCK PWM CONT. WITH 4.5V-28V INPUT,20L - Tape and Reel |
| ISL6420AIRZ-TKS2705 | 制造商:Intersil Corporation 功能描述:CISCO, ISL6420AIRZ-TK W/CONTAINER LABELING, SPECIAL CHANGE C - Rail/Tube |
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