參數(shù)資料
型號: ISL6420A
廠商: Intersil Corporation
英文描述: Advanced Single Synchronous Buck Pulse-Width Modulation (PWM) Controller(單片同步降壓脈寬調(diào)制控制器)
中文描述: 高級單同步降壓脈寬調(diào)制(PWM)控制器(單片同步降壓脈寬調(diào)制控制器)
文件頁數(shù): 13/20頁
文件大小: 560K
代理商: ISL6420A
13
FN9169.1
October 13, 2005
The slew time of the current is set by an external capacitor
on the CDEL pin, which is charged and discharged with a
100μA current source. The change in voltage on the
capacitor is 2.5V. This same capacitor is used to set the
PGOOD active delay after soft-start. When PGOOD is low,
the internal PGOOD circuitry uses the capacitor and when
PGOOD is high, the voltage margining circuit uses the
capacitor. The slew time for voltage margining can be in the
range of 300μs to 2ms.
External Reference/DDR Supply
The voltage margining can be disabled by connecting the
VMSET/MODE to VCC5. In this mode the chip can be
configured to work with an external reference input and
provide a buffered reference output.
If VMSET/MODE pin and the GPIO1/REFIN pin are both tied
to VCC5, then the internal 0.6V reference is used as the
error amplifier non-inverting input. The buffered reference
output on REFOUT will be 0.6V ±0.01V, capable of sourcing
20mA and sinking up to 50μA current with a 2.2μF capacitor
connected to the REFOUT pin.
If VMSET/MODE pin is tied to high but GPIO1/REFIN is
connected to an external voltage source between 0.6V to
1.25V, then this external voltage is used as the reference
voltage at the positive input of the error amplifier. The
buffered reference output on REFOUT will be Vrefin ±0.01V,
capable of sourcing 20mA and sinking up to 50μA current
with a 2.2μF capacitor on the REFOUT pin.
Power Good
The PGOOD pin can be used to monitor the status of the
output voltage. PGOOD will be true (open drain) when the
FB pin is within ±10% of the reference and the ENSS pin has
completed its soft-start ramp.
Additionally, a capacitor on the CDEL pin will set a delay for
the PGOOD signal. After the ENSS pin completes its soft-
start ramp, a 2μA current begins charging the CDEL
capacitor to 2.5V. The capacitor will be quickly discharged
before PGOOD goes high. The programmable delay can be
used to sequence multiple converters or as a LOW-true
reset signal.
If the voltage on the FB pin exceeds ±10% of the reference,
then PGOOD will go low after 1μs of noise filtering.
Over-Temperature Protection
The IC is protected against over-temperature conditions.
When the junction temperature exceeds 150°C, the PWM
shuts off. Normal operation is resumed when the junction
temperature is cooled down to 130°C.
Shutdown
When ENSS pin is below 1V, the regulator is disabled with
the PWM output drivers three-stated. When disabled, the IC
power will be reduced.
FIGURE 11A.
FIGURE 11B.
V
IN
= 12V, V
OUT
= 3.3V, NO LOAD
V
IN
= 12V, V
OUT
= 3.3V, NO LOAD
FIGURE 12. PGOOD DELAY
V
IN
= 12V, V
OUT
= 3.3V, I
OUT
= 10A
ISL6420A
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PDF描述
ISL6420AIAZ-TK Circular Connector; No. of Contacts:22; Series:MS27473; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:12; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:12-35 RoHS Compliant: No
ISL6420IAZ-TK PCB Relay; Contacts:SPDT; Contact Carry Current:500mA; Coil Voltage DC Max:9V; Relay Terminals:SMT Gullwing; Coil Resistance:405ohm; Contact Rating:10mA at 30VAC; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):No RoHS Compliant: Yes
ISL6420IRZ-T Advanced Single Synchronous Buck Pulse-Width Modulation (PWM) Controller
ISL6420IA-TK Advanced Single Synchronous Buck Pulse-Width Modulation (PWM) Controller
ISL6420IAZ Advanced Single Synchronous Buck Pulse-Width Modulation (PWM) Controller
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