參數(shù)資料
型號(hào)： ISL6420
廠商： Intersil Corporation
英文描述： Quadruple 2-Input Positive-AND Gates 14-SOIC -40 to 85
中文描述： 高級(jí)單同步降壓脈寬調(diào)制（PWM）控制器
文件頁(yè)數(shù)： 15/19頁(yè)
文件大小： 525K
代理商： ISL6420
15
FN9151.4
July 18, 2005
Feedback Compensation
Figure 14 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(Vout) is regulated to the Reference voltage level. The error
amplifier (Error Amp) output (V
E/A
) is compared with the
oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of V
IN
at the
PHASE node. The PWM wave is smoothed by the output filter
(L
O
and C
O
).
The modulator transfer function is the small-signal transfer
function of Vout/V
E/A
. This function is dominated by a DC
Gain and the output filter (L
O
and C
O
), with a double pole
break frequency at F
LC
and a zero at F
ESR
. The DC Gain of
the modulator is simply the input voltage (V
IN
) divided by the
peak-to-peak oscillator voltage DV
OSC
.
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6420) and the impedance networks Z
IN
and Z
FB
. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f
0dB
) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f
0dB
and
180
o
. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 14. Use these guidelines for
locating the poles and zeros of the compensation network:
Compensation Break Frequency Equations
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
ST
Zero Below Filter’s Double Pole
(~75% F
LC
)
3. Place 2
ND
Zero at Filter’s Double Pole
4. Place 1
ST
Pole at the ESR Zero
5. Place 2
ND
Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Figure 15
shows an asymptotic plot of the DC/DC
converter’s gain vs. frequency. The actual Modulator Gain
has a high gain peak do to the high Q factor of the output
filter and is not shown in Figure 15. Using the above
guidelines should give a Compensation Gain similar to the
curve plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F
P2
with the capabilities of the error amplifier. The Closed Loop
Gain is constructed on the log-log graph of Figure 15 by
adding the Modulator Gain (in dB) to the Compensation Gain
(in dB). This is equivalent to multiplying the modulator
transfer function to the compensation transfer function and
plotting the gain.
FIGURE 14. VOLTAGE - MODE BUCK CONVERTER
COMPENSATION DESIGN
V
OUT
OSC
REFERENCE
L
O
C
O
ESR
V
IN
V
OSC
ERROR
AMP
PWM
DRIVER
(PARASITIC)
-
+
REF
R1
R3
R2
C3
C2
C1
COMP
V
OUT
FB
Z
FB
ISL6420
Z
IN
COMPARATOR
DRIVER
DETAILED COMPENSATION COMPONENTS
PHASE
V
E/A
+
-
+
-
Z
IN
Z
FB
F
LC
L
O
2
π
C
O
--------------------------------------
=
(EQ. 4)
F
ESR
O
)
--------------------------------------------
=
(EQ. 5)
F
Z1
----------------------------------
=
(EQ. 6)
F
P1
2
π
R2
C1
C2
+
----------------------
------------------------------------------------------
=
(EQ. 7)
F
Z2
R3
)
C3
-------------------------+
=
(EQ. 8)
F
P2
=
----------------------------------
(EQ. 9)
ISL6420
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