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參數(shù)資料
| 型號： | ISL6296 |
| 廠商： | Intersil Corporation |
| 英文描述： | FlexiHash For Battery Authentication |
| 中文描述： | FlexiHash對于電池認證 |
| 文件頁數(shù)： | 12/17頁 |
| 文件大?。?/td> | 384K |
| 代理商： | ISL6296 |
12
FN9201.0
February 1, 2005
Bus Transaction Protocol
The XSD bus for the ISL6296 defines three types of bus
transactions. Figure 11 shows the bus transaction protocol.
The blue color represents the signal sent by the host and the
green color stands for the signal sent by the device. Before
the transaction starts, the host should make sure that the
XSD device is not in the sleep mode. One method is to
always send a ‘break’ signal before starting the transaction,
as shown in Figure 11. If the device is not in the sleep mode,
the ‘break’ signal is not mandatory. The ‘break’ pulse width
may appear to be wider than what the host sends out
because of the reason explained in Figure 4. The symbols in
Figure 11 are explained in Table 7.
Passive CRC Support
The CRC feature only supports the read transaction in the
ISL6296. When the OPCODE in the instruction is ‘10’, an
8-bit CRC is automatically calculated for the data bytes
being transferred out. The CRC result is then appended after
the last data byte is read out.
CRC is generated using the DOW CRC polynomial as
follows:
Polynom = 1 + X
4
+ X
5
+ X
8
The CRC generation algorithm is logically illustrated in
Figure 12. Prior to a new CRC calculation, the LFSR (linear
feedback shift register) is initialized to zero. The read data to
be transmitted out is concurrently shifted into the CRC
calculator. After the actual data is transmitted out, the final
content of the LFSR is the resulting CRC value. This value is
transmitted out after the read data, with LSB being
transmitted out first.
TABLE 7. SYMBOLS IN THE BUS TRANSACTION PROTOCOL
SYM
DESCRIPTION
MIN
TYP
MAX
IFG
H
Host inter-frame gap
0 BT
H
800ms
IFG
D
Device inter-frame gap
1 BT
D
TA
H
Host turn-around time
1 BT
H
800ms
TA
D
Device turn-around time
1 BT
D
FIGURE 11. XSD BUS TRANSACTION PROTOCOL. THE ‘BREAK’ SIGNAL IS OPTIONAL IF THE DEVICE IS AWAKE
IFGH
H
Write Instruction Frame
Data Frame 1
Data Frame 2
IFG
break
T
SD
TAD
Read Instruction Frame
Data Frame 1
(output from slave)
(output from slave)
Data Frame 2
IFGD
break
T
SD
(output from slave)
D
H
Read Instruction Frame
Data Frame
Next Instruction
Frame
TA
TAH
break
T
SD
(A) Multi-Byte Write Instruction.
(B) Multi-Byte Read Instruction.
(C) Back-to-Back Transaction (Read Followed by Write).
FIGURE 12. THE CRC CALCULATOR FOR THE PASSIVE CRC SUPPORT
1st
Stage
2nd
Stage
3rd
Stage
4th
Stage
5th
Stage
7th
Stage
8th
Stage
Serial
Output
6th
Stage
LSB
MSB
ISL6296
相關PDF資料 |
PDF描述 |
|---|---|
| ISL6296DH-T | FlexiHash For Battery Authentication |
| ISL6296EVAL1 | FlexiHash For Battery Authentication |
| ISL6296DHZ-T | FlexiHash For Battery Authentication |
| ISL6297 | Li-ion/Li Polymer Battery Charger |
| ISL6297CR-T | Li-ion/Li Polymer Battery Charger |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISL6296_07 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:FlexiHash⑩ For Battery Authentication |
| ISL6296_08 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:FlexiHash⑩ For Battery Authentication |
| ISL6296A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:FlexiHash⑩ For Battery Authentication |
| ISL6296ADHZ-T | 功能描述:IC AUTHENTICATION DEVICE SOT23-5 RoHS:是 類別:集成電路 (IC) >> PMIC - 電池管理 系列:FlexiHash™ 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 功能:電池監(jiān)控器 電池化學:堿性，鋰離子，鎳鎘，鎳金屬氫化物 電源電壓:1 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-6 包裝:帶卷 (TR) |
| ISL6296ADRTZ-T | 功能描述:IC AUTHENTICATION DEVICE 8-TDFN RoHS:是 類別:集成電路 (IC) >> PMIC - 電池管理 系列:FlexiHash™ 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 功能:電池監(jiān)控器 電池化學:堿性，鋰離子，鎳鎘，鎳金屬氫化物 電源電壓:1 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-6 包裝:帶卷 (TR) |
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