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參數(shù)資料
| 型號： | ISL6211CA-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Crusoe⑩ Processor Core-Voltage Regulator |
| 中文描述： | SWITCHING CONTROLLER, 690 kHz SWITCHING FREQ-MAX, PDSO24 |
| 封裝： | PLASTIC, SSOP-24 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 257K |
| 代理商： | ISL6211CA-T |
9
Output Voltage Droop
An output voltage ’droop’ or an active voltage positioning is
now widely used in the computer power applications. The
technique is based on raising the converter voltage at light
load in anticipation of a possible load current step, Figure 4.
Conversely, the output voltage is lowered at high load in
anticipation of possible load drop. The output voltage varies
with the load as if a resistor were connected in series with
the converter’s output. When done as a part of the feedback
in a closed loop, the droop is not associated with substantial
power losses, though, because there is no such resistor in
the real circuit, rather the feature is emulated through
feedback.
To get the most from the droop, its value should be scaled
with capacitor’s ESR voltage drop.
V
DROOP
=
As Figure 5 shows, droop allows reduced size and cost of
the output capacitors required to handle CPU current
transients.
The reduction may be almost two times when compared to a
system without the droop. Additionally, the CPU power
dissipation is also slightly reduced as it is proportional to the
applied voltage squared and even slight voltage decrease
translates in a measurable reduction in power dissipated.
The Crusoe processor regulation window including
transients is specified as +5%...-2%. To accommodate the
droop, the output voltage of the converter is raised ~3.5% at
no load conditions as it is shown in the Figure 6.
The value of the resistor connected between the ISEN pin
and the drain of the lower MOSFET sets the droop value.;
Where, V
DROOP
is a desired value of the droop at maximum
CPU current, I
MAX
is a peak value of the inductor current in
maximum load, R
DS(ON)
is a lower MOSFET impedance in
conducting state.
The converter response to a load step is shown in the Figure
7. At zero load current, the output voltage is raised ~50mV
above nominal value of 1.35V. When the load current
increases, the output voltage droops down approximately
55mV. Due to use of droop, the converter’s output voltage
adoptively changes with the load current allowing better
utilization of the regulation window.
Operation Mode Control
R3
V
DSX
R1
REF
10
μ
A
----------------–
=
FIGURE 4. OUTPUT VOLTAGE DROOP
0
I
MAX
1.2V
I
CPU
V
CPU
VID CODE PROGRAMMED VOLTAGE
V
DROOP
LOAD LINE
I
MAX
ESR
FIGURE 5. ADAPTIVE VOLTAGE POSITIONING
a)
b)
c)
I
o
V
ESR
NO DROOP
V
ESR
~ V
DROOP
FIGURE 6. SETTING THE OUTPUT VOLATGE RISE AT NO
LOAD CONDITIONS
R1
R2
VSEN
ISL6211
16
V
OUT
Vrise,% = R1/(R1+R2)
R
CS
2083
---------------------------------------------------------------
I
DROOP
R
)
100
–
=
FIGURE 7. CONVERTER RESPONSE TO LOAD STEP
CH1 50mV
CH2 2.0A
M50
μ
s
1
2
V
CPU
= 1.35V
I
CPU
= 0A...5.0A
UPPER LIMIT
LOWER LIMIT
ISL6211
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