參數(shù)資料
型號: ISL6208CRZ
廠商: INTERSIL CORP
元件分類: 功率晶體管
英文描述: High Voltage Synchronous Rectified Buck MOSFET Driver
中文描述: 4 A HALF BRDG BASED MOSFET DRIVER, PQCC8
封裝: 3 X 3 MM, ROHS COMPLIANT, PLASTIC, MO-220, QFN-8
文件頁數(shù): 5/10頁
文件大小: 325K
代理商: ISL6208CRZ
5
Functional Pin Description
UGATE (Pin 1 for SOIC-8, Pin 8 for QFN)
The UGATE pin is the upper gate drive output. Connect to
the gate of high-side power N-Channel MOSFET.
BOOT (Pin 2 for SOIC-8, Pin 1 for QFN)
BOOT is the floating bootstrap supply pin for the upper gate
drive. Connect the bootstrap capacitor between this pin and
the PHASE pin. The bootstrap capacitor provides the charge
to turn on the upper MOSFET. See the Bootstrap Diode and
Capacitor section under DESCRIPTION for guidance in
choosing the appropriate capacitor value.
PWM (Pin 3 for SOIC-8, Pin 2 for QFN)
The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation (see
the three-state PWM Input section under DESCRIPTION for
further details). Connect this pin to the PWM output of the
controller.
GND (Pin 4 for SOIC-8, Pin 3 for QFN)
GND is the ground pin for the IC.
LGATE (Pin 5 for SOIC-8, Pin 4 for QFN)
LGATE is the lower gate drive output. Connect to gate of the
low-side power N-Channel MOSFET.
VCC (Pin 6 for SOIC-8, Pin 5 for QFN)
Connect the VCC pin to a +5V bias supply. Place a high
quality bypass capacitor from this pin to GND.
FCCM (Pin 7 for SOIC-8, Pin 6 for QFN)
The FCCM pin enables or disables Diode Emulation. When
FCCM is LOW, diode emulation is allowed. Otherwise,
continuous conduction mode is forced. See the Diode
Emulation section under DESCRIPTION for more detail.
PHASE (Pin 8 for SOIC-8, Pin 7 for QFN)
Connect the PHASE pin to the source of the upper MOSFET
and the drain of the lower MOSFET. This pin provides a
return path for the upper gate driver.
Description
Theory of Operation
Designed for speed, the ISL6208 dual MOSFET driver
controls both high-side and low-side N-Channel FETs from
one externally provided PWM signal.
A rising edge on PWM initiates the turn-off of the lower
MOSFET (see Timing Diagram). After a short propagation
delay [t
PDLL
], the lower gate begins to fall. Typical fall times
[t
FL
] are provided in the Electrical Specifications section.
Adaptive shoot-through circuitry monitors the LGATE
voltage. When LGATE has fallen below 1V, UGATE is
allowed to turn ON. This prevents both the lower and upper
MOSFETs from conducting simultaneously, or shoot-
through.
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t
PDLU
] is encountered before the upper
gate begins to fall [t
FU
]. The upper MOSFET gate-to-source
voltage is monitored, and the lower gate is allowed to rise
after the upper MOSFET gate-to-source voltage drops below
1V. The lower gate then rises [t
RL
], turning on the lower
MOSFET.
VCC
PWM
10K
CONTROL
LOGIC
SHOOT-
THROUGH
PROTECTION
BOOT
UGATE
PHASE
LGATE
GND
VCC
FCCM
THERMAL PAD (FOR QFN PACKAGE ONLY)
FIGURE 1. BLOCK DIAGRAM
ISL6208
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