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參數(shù)資料
| 型號(hào)： | ISL6208CR |
| 廠商： | INTERSIL CORP |
| 元件分類(lèi)： | 功率晶體管 |
| 英文描述： | Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputs 20-SOIC -40 to 85 |
| 中文描述： | 4 A HALF BRDG BASED MOSFET DRIVER, PQCC8 |
| 封裝： | 3 X 3 MM, PLASTIC, MO-220, QFN-8 |
| 文件頁(yè)數(shù)： | 9/10頁(yè) |
| 文件大?。?/td> | 325K |
| 代理商： | ISL6208CR |
9
Quad Flat No-Lead Plastic Package (QFN)
L8.3x3
8 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VEEC ISSUE C)
SYMBOL
MILLIMETERS
NOTES
MIN
NOMINAL
MAX
A
0.80
0.90
1.00
-
A1
-
-
0.05
-
A2
-
-
1.00
9
A3
0.20 REF
9
b
0.23
0.28
0.38
5, 8
D
3.00 BSC
-
D1
2.75 BSC
9
D2
0.25
1.10
1.25
7, 8
E
3.00 BSC
-
E1
2.75 BSC
9
E2
0.25
1.10
1.25
7, 8
e
0.65 BSC
-
k
0.25
-
-
L
0.35
0.60
0.75
8
L1
-
-
0.15
10
N
8
2
Nd
2
3
Ne
2
3
P
-
-
0.60
9
θ
-
-
12
9
Rev. 1 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P &
θ
are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
ISL6208
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