參數(shù)資料
型號(hào)： ISL6207CBZ-T
廠商： INTERSIL CORP
元件分類： MOSFETs
英文描述： High Voltage Synchronous Rectified Buck MOSFET Driver
中文描述： 4 A HALF BRDG BASED MOSFET DRIVER, PDSO8
封裝： ROHS COMPLIANT, PLASTIC, SOIC-8
文件頁(yè)數(shù)： 4/9頁(yè)
文件大?。?/td> 292K
代理商： ISL6207CBZ-T
4
FN9075.7
July 25, 2005
Functional Pin Description
UGATE (Pin 1 for SOIC-8, Pin 8 for QFN)
The UGATE pin is the upper gate drive output. Connect to
the gate of high-side power N-Channel MOSFET.
BOOT (Pin 2 for SOIC-8, Pin 1 for QFN)
BOOT is the floating bootstrap supply pin for the upper gate
drive. Connect the bootstrap capacitor between this pin and
the PHASE pin. The bootstrap capacitor provides the charge
to turn on the upper MOSFET. See the Bootstrap Diode and
Capacitor section under DESCRIPTION for guidance in
choosing the appropriate capacitor value.
PWM (Pin 3 for SOIC-8, Pin 2 for QFN)
The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation, see the
three-state PWM Input section under DESCRIPTION for further
details. Connect this pin to the PWM output of the controller. In
addition, place a 500k
resistor to ground from this pin. This
allows for proper three-state operation under all start-up
conditions.
GND (Pin 4 for SOIC-8, Pin 3 for QFN)
GND is the ground pin. All signals are referenced to this node.
LGATE (Pin 5 for SOIC-8, Pin 4 for QFN)
LGATE is the lower gate drive output. Connect to gate of the
low-side power N-Channel MOSFET.
VCC (Pin 6 for SOIC-8, Pin 5 for QFN)
Connect the VCC pin to a +5V bias supply. Place a high
quality bypass capacitor from this pin to GND.
EN (Pin 7 for SOIC-8, Pin 6 for QFN)
EN is the enable input pin. Connect this pin to HIGH to
enable, and LOW to disable, the IC. When disabled, the IC
draws less than 1
μ
A bias current.
PHASE (Pin 8 for SOIC-8, Pin 7 for QFN)
Connect the PHASE pin to the source of the upper MOSFET
and the drain of the lower MOSFET. This pin provides a
return path for the upper gate driver.
Description
Operation
Designed for speed, the ISL6207 dual MOSFET driver
controls both high-side and low-side N-Channel FETs from
one externally provided PWM signal.
A rising edge on PWM initiates the turn-off of the lower
MOSFET (see Timing Diagram). After a short propagation
delay [t
PDLLGATE
], the lower gate begins to fall. Typical fall
times [t
FLGATE
] are provided in the Electrical Specifications
section. Adaptive shoot-through circuitry monitors the LGATE
voltage and determines the upper gate delay time
[t
PDHUGATE
], based on how quickly the LGATE voltage drops
below 1V. This prevents both the lower and upper MOSFETs
from conducting simultaneously, or shoot-through. Once this
delay period is completed, the upper gate drive begins to rise
[t
RUGATE
], and the upper MOSFET turns on.
UGATE Turn-On Propagation Delay
t
PDHUGATE
V
VCC
= 5V, Outputs Unloaded
10
20
30
ns
LGATE Turn-On Propagation Delay
t
PDHLGATE
V
VCC
= 5V, Outputs Unloaded
10
20
30
ns
OUTPUT
Upper Drive Source Resistance
R
UGATE
500mA Source Current
-
1.0
2.5
-10°C to 85°C
-
1.0
2.2
Upper Driver Source Current (Note 5)
I
UGATE
V
UGATE-PHASE
= 2.5V
-
2.0
-
A
Upper Drive Sink Resistance
R
UGATE
500mA Sink Current
-
1.0
2.5
-10°C to 85°C
-
1.0
2.2
Upper Driver Sink Current (Note 5)
I
UGATE
V
UGATE-PHASE
= 2.5V
-
2.0
-
A
Lower Drive Source Resistance
R
LGATE
500mA Source Current
-
1.0
2.5
-10°C to 85°C
-
1.0
2.2
Lower Driver Source Current (Note 5)
I
LGATE
V
LGATE
= 2.5V
-
2.0
-
A
Lower Drive Sink Resistance
R
LGATE
500mA Sink Current
-
0.4
1.0
-10°C to 85°C
-
0.4
0.8
Lower Driver Sink Current (Note 5)
I
LGATE
V
LGATE
= 2.5V
-
4.0
-
A
NOTE:
5. Guaranteed by characterization, not 100% tested in production.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted.
(Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ISL6207
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