Digital Supply Voltage DVDD to DGND . . " />
參數(shù)資料
型號(hào)： ISL5929INZ
廠商： Intersil
文件頁(yè)數(shù)： 9/13頁(yè)
文件大?。?/td> 0K
描述： IC DAC 14BIT CMOS DUAL 48LQFP
標(biāo)準(zhǔn)包裝： 250
位數(shù)： 14
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 274mW
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 托盤(pán)
輸出數(shù)目和類(lèi)型： *
采樣率（每秒）： 150M
5
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage DVDD to DGND . . . . . . . . . . . . . . . . . . +3.6V
Analog Supply Voltage AVDD to AGND . . . . . . . . . . . . . . . . . . +3.6V
Grounds, AGND TO DGND . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (DATA, CLK, SLEEP). . . . . . . . . DVDD + 0.3V
Reference Input Voltage Range . . . . . . . . . . . . . . . . . . AVDD + 0.3V
Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
Thermal Resistance (Typical, Note 1)
θJA(°C/W)
LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AVDD = DVDD = +3.3V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25°C for All Typical Values
PARAMETER
TEST CONDITIONS
TA = -40°C TO 85°C
UNITS
MIN
TYP
MAX
SYSTEM PERFORMANCE
Resolution
14
-
Bits
Integral Linearity Error, INL
“Best Fit” Straight Line (Note 7)
-5
±2.5
+5
LSB
Differential Linearity Error, DNL
(Note 7)
-3
±1.5
+3
LSB
Offset Error, IOS
IOUTA (Note 7)
-0.006
+0.006
% FSR
Offset Drift Coefficient
(Note 7)
-
0.1
-
ppm
FSR/°C
Full Scale Gain Error, FSE
With External Reference (Notes 2, 7)
-3
±0.5
+3
% FSR
With Internal Reference (Notes 2, 7)
-3
±0.5
+3
% FSR
Full Scale Gain Drift
With External Reference (Note 7)
-
±50
-
ppm
FSR/°C
With Internal Reference (Note 7)
-
±100
-
ppm
FSR/°C
Crosstalk
fCLK = 100MSPS, fOUT = 10MHz
-
83
-
dB
fCLK = 100MSPS, fOUT = 40MHz
-
74
-
dB
Gain Matching Between Channels
(DC Measurement)
As a percentage of Full Scale Range
-1.6
0.6
+1.6
% FSR
In dB Full Scale Range
-0.14
0.05
+0.14
dB FSR
Full Scale Output Current, IFS
220
22
mA
Output Voltage Compliance Range
(Note 3)
-1.0
-
1.25
V
DYNAMIC CHARACTERISTICS
Maximum Clock Rate, fCLK
ISL5929/2IN
210
250
-
MHz
Maximum Clock Rate, fCLK
ISL5929IN
130
150
-
MHz
Output Rise Time
Full Scale Step
-
1
-
ns
Output Fall Time
Full Scale Step
-
1
-
ns
Output Capacitance
-5
-
pF
Output Noise
IOUTFS = 20mA
-
50
-
pA/
√Hz
IOUTFS = 2mA
-
30
-
pA/
√Hz
ISL5929
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