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參數(shù)資料
| 型號： | ISL5929IN |
| 廠商： | INTERSIL CORP |
| 元件分類： | DAC |
| 英文描述： | Dual 14-Bit, +3.3V, 130/210MSPS, CommLink TM High Speed D/A Converter |
| 中文描述： | DUAL, PARALLEL, WORD INPUT LOADING, 14-BIT DAC, PQFP48 |
| 封裝： | 7 X 7 MM, PLASTIC, MS-026-BBC, LQFP-48 |
| 文件頁數(shù)： | 10/13頁 |
| 文件大?。?/td> | 844K |
| 代理商： | ISL5929IN |
10
Definition of Specifications
Adjacent Channel Power Ratio, ACPR,
is the ratio of the
average power in the adjacent frequency channel (or offset)
to the average power in the transmitted frequency channel.
Crosstalk,
is the measure of the channel isolation from one
DAC to the other. It is measured by generating a sinewave in
one DAC while the other DAC is clocked with a static input,
and comparing the output power of each DAC at the
frequency generated.
Differential Linearity Error, DNL,
is the measure of the
step size output deviation from code to code. Ideally the step
size should be one LSB. A DNL speci
fi
cation of one LSB or
less guarantees monotonicity.
EDGE, Enhanced Data for Global Evolution,
a TDMA
standard for cellular applications which uses 200kHz BW,
8-PSK modulated carriers.
Full Scale Gain Drift,
is measured by setting the data inputs
to be all logic high (all 1s) and measuring the output voltage
through a known resistance as the temperature is varied
from T
MIN
to T
MAX
. It is de
fi
ned as the maximum
deviation
from the
value
measured at room temperature to the
value
measured at either T
MIN
or T
MAX
. The units are ppm of FSR
(full scale range) per °C.
Full Scale Gain Error,
is the error from an ideal ratio of 32
between the output current and the full scale adjust current
(through R
SET
).
Gain Matching,
is a measure of the full scale amplitude
match between the I and Q channels given the same input
pattern. It is typically measured with all 1s at the input to
both channels, and the full scale output voltage developed
into matching loads is compared for the I and Q outputs.
GSM, Global System for Mobile Communication,
a TDMA
standard for cellular applications which uses 200kHz BW,
GMSK modulated carriers.
Integral Linearity Error, INL,
is the measure of the worst
case point that deviates from a best
fi
t straight line of data
values along the transfer curve.
Internal Reference Voltage Drift,
is
de
fi
ned as the
maximum
deviation
from the
value
measured at room
temperature to the
value
measured at either T
MIN
or T
MAX
.
The units are ppm per °C.
Offset Drift,
is measured by setting the data inputs to all
logic low (all 0s) and measuring the output voltage at IOUTA
through a known resistance as the temperature is varied
from T
MIN
to T
MAX
.
It is de
fi
ned as the maximum
deviation
from the
value
measured at room temperature to the
value
measured at either T
MIN
or T
MAX
. The units are ppm of FSR
(full scale range) per degree °C.
Offset Error,
is measured by setting the data inputs to all
logic low (all 0s) and measuring the output voltage of IOUTA
through a known resistance. Offset error is de
fi
ned as the
maximum
deviation
of the IOUTA output current from a value
of 0mA.
Output Voltage Compliance Range,
is the voltage limit
imposed on the output. The output impedance should be
chosen such that the voltage developed does not violate the
compliance range.
Power Supply Rejection,
is measured using a single power
supply. The nominal supply voltage is varied
±
10% and the
change in the DAC full scale output is noted.
Reference Input Multiplying Bandwidth,
is
de
fi
ned as the
3dB bandwidth of the voltage reference input. It is measured
by using a sinusoidal waveform as the external reference
with the digital inputs set to all 1s. The frequency is
increased until the amplitude of the output waveform is 0.707
(-3dB) of its original value.
Spurious Free Dynamic Range, SFDR
, is the amplitude
difference from the fundamental signal to the largest
harmonically or non-harmonically related spur within the
speci
fi
ed frequency window.
Total Harmonic Distortion, THD,
is the ratio of the RMS
value of the fundamental output signal to the RMS sum of
the
fi
rst
fi
ve harmonic components.
UMTS, Universal Mobile Telecommunications System,
a
W-CDMA standard for cellular applications which uses
3.84MHz modulated carriers.
Detailed Description
The ISL5929 is a dual 14-bit, current out, CMOS, digital to
analog converter. The core of each DAC is based on the
ISL5961. The maximum update rate is at least 210+MSPS
and can be powered by a single power supply in the
recommended range of +3.0V to +3.6V. Operation with clock
rates higher than 210MSPS is possible; please contact the
factory for more information. It consumes less than 125mW
of power per channel when using a +3.3V supply, the
maximum 20mA of output current, and the data switching at
210MSPS. The architecture is based on a segmented
current source arrangement that reduces glitch by reducing
the amount of current switching at any one time. In previous
architectures that contained all binary weighted current
sources or a binary weighted resistor ladder, the converter
might have a substantially larger amount of current turning
on and off at certain, worst-case transition points such as
midscale and quarter scale transitions. By greatly reducing
the amount of current switching at these major transitions,
the overall glitch of the converter is dramatically reduced,
improving settling time, transient problems, and accuracy.
Digital Inputs and Termination
The ISL5929 digital inputs are formatted as offset binary and
guaranteed to 3V LVCMOS levels. The internal register is
updated on the rising edge of the clock. To minimize
ISL5929
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