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參數資料
| 型號： | ISL5861IB |
| 廠商： | INTERSIL CORP |
| 元件分類： | DAC |
| 英文描述： | 12-bit, +3.3V, 130/210MSPS, CommLinkTM High Speed D/A Converter |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 12-BIT DAC, PDSO28 |
| 封裝： | PLASTIC, MS-013AE, SOIC-28 |
| 文件頁數： | 11/13頁 |
| 文件大小： | 906K |
| 代理商： | ISL5861IB |
11
Propagation Delay
The converter requires two clock rising edges for data to be
represented at the output. Each rising edge of the clock
captures the present data word and outputs the previous
data. The propagation delay is therefore 1/CLK, plus <2ns of
processing. See Figure 15.
Test Service
Intersil offers customer-specific testing of CommLink
converters with a service called Testdrive. To submit a
request, fill out the Testdrive form. The form can be found by
doing an ‘entire site search’ at www.intersil.com on the
words ‘DAC Testdrive’. Or, send a request to the technical
support center.
FIGURE 13. OUTPUT LOADING FOR DATASHEET
MEASUREMENTS
PIN 21
PIN 22
ISL5861
R
DIFF
R
LOAD
IOUTB
IOUTA
V
OUT
= (2 x IOUTA x R
EQ
)V
1:1
L
OAD SEEN BY THE TRANSFORMER
R
LOAD
REPRESENTS THE
R
EQ
= 0.5 x (R
LOAD
// R
DIFF
)
AT EACH OUTPUT
FIGURE 14. ALTERNATIVE OUTPUT LOADING
PIN 21
PIN 22
ISL5861
IOUTB
IOUTA
V
OUT
= (2 x IOUTA x R
EQ
)V
R
EQ
= 0.5 x (R
LOAD
// R
DIFF
// R
A
), WHERE R
A
=R
B
AT EACH OUTPUT
R
LOAD
R
DIFF
R
A
R
B
LOAD SEEN BY THE TRANSFORMER
R
LOAD
REPRESENTS THE
Timing Diagram
FIGURE 15. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
CLK
I
OUT
50%
t
PW1
t
PW2
t
SU
t
HLD
t
SU
t
SU
t
PD
t
HLD
t
HLD
D11-D0
W
0
W
1
W
2
W
3
OUTPUT=W
0
OUTPUT=W
1
t
PD
OUTPUT=W
-1
ISL5861
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