參數(shù)資料
型號： ISL5761IBZ
廠商： INTERSIL CORP
元件分類： DAC
英文描述： 10-bit, +3.3V, 130/210+MSPS, High Speed D/A Converter
中文描述： PARALLEL, WORD INPUT LOADING, 10-BIT DAC, PDSO28
封裝： LEAD FREE, PLASTIC, MS-013AE, SOIC-28
文件頁數(shù)： 5/13頁
文件大小： 575K
代理商： ISL5761IBZ
5
Spurious Free Dynamic Range,
SFDR to Nyquist (f
CLK
/2)
f
CLK
= 210MSPS, f
OUT
= 80.8MHz (Notes 4, 7)
-
50
-
dBc
f
CLK
= 210MSPS, f
OUT
= 40.4MHz (Notes 4, 7, 9)
f
CLK
= 200MSPS, f
OUT
= 20.2MHz, T = 25
o
C (Notes 4, 7)
f
CLK
= 200MSPS, f
OUT
= 20.2MHz, T = -40
o
C to 85
o
C (Notes 4, 7)
-
58
-
dBc
58
60
-
dBc
56
-
-
dBc
f
CLK
= 130MSPS, f
OUT
= 50.5MHz (Notes 4, 7)
-
55
-
dBc
f
CLK
= 130MSPS, f
OUT
= 40.4MHz (Notes 4, 7)
-
60
-
dBc
f
CLK
= 130MSPS, f
OUT
= 20.2MHz (Notes 4, 7)
-
68
-
dBc
f
CLK
= 130MSPS, f
OUT
= 10.1MHz (Notes 4, 7)
f
CLK
= 130MSPS, f
OUT
= 5.05MHz, T = 25
o
C (Notes 4, 7)
f
CLK
= 130MSPS, f
OUT
= 5.05MHz, T = -40
o
C to 85
o
C (Notes 4, 7)
-
70
-
dBc
68
75
-
dBc
66
-
-
dBc
f
CLK
= 100MSPS, f
OUT
= 40.4MHz (Notes 4, 7)
-
58
-
dBc
f
CLK
= 80MSPS, f
OUT
= 30.3MHz (Notes 4, 7)
-
61
-
dBc
f
CLK
= 80MSPS, f
OUT
= 20.2MHz (Notes 4, 7)
-
67
-
dBc
f
CLK
= 80MSPS, f
OUT
= 10.1MHz (Notes 4, 7, 9)
-
69
-
dBc
f
CLK
= 80MSPS, f
OUT
= 5.05MHz (Notes 4, 7)
-
74
-
dBc
f
CLK
= 50MSPS, f
OUT
= 20.2MHz (Notes 4, 7)
-
66
-
dBc
f
CLK
= 50MSPS, f
OUT
= 10.1MHz (Notes 4, 7)
-
72
-
dBc
f
CLK
= 50MSPS, f
OUT
= 5.05MHz (Notes 4, 7)
-
75
-
dBc
Spurious Free Dynamic Range,
SFDR in a Window with Eight Tones
f
CLK
= 210MSPS, f
OUT
= 28.3MHz to 45.2MHz, 2.1MHz Spacing,
50MHz Span (Notes 4, 7, 9)
-
63
-
dBc
f
CLK
= 130MSPS, f
OUT
=17.5MHz to 27.9MHz, 1.3MHz Spacing,
35MHz Span (Notes 4, 7)
-
66
-
dBc
f
CLK
= 80MSPS, f
OUT
= 10.8MHz to 17.2MHz, 811kHz Spacing,
15MHz Span (Notes 4, 7)
-
73
-
dBc
f
CLK
= 50MSPS, f
OUT
= 6.7MHz to 10.8MHz, 490kHz Spacing,
10MHz Span (Notes 4, 7)
-
75
-
dBc
Spurious Free Dynamic Range,
SFDR in a Window with EDGE or GSM
f
CLK
= 78MSPS, f
OUT
= 11MHz, in a 20MHz Window, RBW=30kHz
(Notes 4, 7, 9)
-
83
-
dBc
Adjacent Channel Power Ratio,
ACPR with UMTS
f
CLK
= 76.8MSPS, f
OUT
= 19.2MHz, RBW=30kHz (Notes 4, 7, 9)
-
65
-
dB
VOLTAGE REFERENCE
Internal Reference Voltage, V
FSADJ
Pin 18 Voltage with Internal Reference
1.2
1.23
1.3
V
Internal Reference Voltage Drift
-
±
40
-
ppm/
o
C
Internal Reference Output Current
Sink/Source Capability
Reference is not intended to be externally loaded (REFIO pin)
-
0
-
μ
A
Reference Input Impedance
-
1
-
M
Reference Input Multiplying Bandwidth (Note 7)
-
1.0
-
MHz
DIGITAL INPUTS
D9-D0, CLK
Input Logic High Voltage with
3.3V Supply, V
IH
(Note 3)
2.3
3.3
-
V
Input Logic Low Voltage with
3.3V Supply, V
IL
(Note 3)
-
0
1.0
V
Sleep Input Current, I
IH
-25
-
+25
μ
A
Electrical Specifications
AV
DD
= DV
DD
= +3.3V, V
REF
= Internal 1.2V, IOUTFS = 20mA, T
A
= 25
o
C for All Typical Values
(Continued)
PARAMETER
TEST CONDITIONS
T
A
= -40
o
C TO 85
o
C
UNITS
MIN
TYP
MAX
ISL5761
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