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參數(shù)資料
| 型號： | ISL5729 |
| 廠商： | Intersil Corporation |
| 英文描述： | Dual 10-bit, +3.3V, 130/210+MSPS, High Speed D/A Converter(雙路10位, +3.3V, 130/210+MSPS, 高速D/A轉(zhuǎn)換器) |
| 中文描述： | 雙10位，3.3伏，二百十分之一百三MSPS的高速D / A轉(zhuǎn)換器（雙路10位，3.3伏，二百十分之一百三MSPS的，高速的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 4/13頁 |
| 文件大?。?/td> | 584K |
| 代理商： | ISL5729 |
4
Pin Descriptions
PIN NO.
PIN NAME
PIN DESCRIPTION
11, 19, 26
AGND
Analog ground.
13, 24
A
VDD
Analog supply (+2.7V to +3.6V).
28
CLK
Clock input.
27
DGND
Connect to digital ground.
10
D
VDD
Digital supply (+2.7V to +3.6V).
20
FSADJ
Full scale current adjust. Use a resistor to ground to adjust full scale output current. Full scale output
current = 32 x V
FSADJ
/R
SET
.
14, 23
NC
Not internally connected. Recommend no connect.
12, 25
ICOMP, QCOMP
Compensation pin for internal bias generation. Each pin should be individually decoupled to AGND with
a 0.1
μ
F capacitor.
1-4, 29-38,
43-48
ID9-ID0, QD9-QD0
Digital data input ports. Bit 9 is most significant bit (MSB) and bit 0 is the least significant bit (LSB).
15, 22
IOUTA, QOUTA
Current outputs of the device. Full scale output current is achieved when all input bits are set to binary 1.
16, 21
IOUTB, QOUTB
Complementary current outputs of the device. Full scale output current is achieved on the complementary
outputs when all input bits are set to binary 0.
17
REFIO
Reference voltage input if Internal reference is disabled. The internal reference is not intended to drive an
external load. Use 0.1
μ
F cap to ground when internal reference is enabled.
18
REFLO
Connect to analog ground to enable internal 1.2V reference or connect to AV
DD
to disable internal reference.
5-8, 39-42
NC
No connect (NC). Not internally connected. No termination required, may be used for device migration to
higher resolution DACs.
9
SLEEP
Connect to digital ground or leave floating for normal operation. Connect to DV
DD
for sleep mode.
ISL5729
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