參數(shù)資料
型號: ISL5585GCR
廠商: INTERSIL CORP
元件分類: 模擬傳輸電路
英文描述: 3.3V Ringing SLIC Family for Voice Over Broadband VOB
中文描述: TELECOM-SLIC, PQCC32
封裝: 7 X 7 MM, PLASTIC, MO-220VKKC, QFN-32
文件頁數(shù): 20/22頁
文件大?。?/td> 425K
代理商: ISL5585GCR
20
Special Considerations for the QFN
Package
The new Quad Flatpack No-lead (QFN) package offers a
significant footprint reduction (65%) and improved thermal
performance with respect to the 28 lead PLCC. To realize
the thermal enhancements and maintain the high voltage
(-100V) performance, the exposed pad on the bottom of the
QFN package should be soldered to a power/heat sink plane
that is electrically connected to the ISL5585
S
ubstrate
C
ommon
C
onnection (SCC) pin. The heat is distributed
evenly across the board by way of the heat sink plane. This
is accomplished by using conductive thermal vias.
Reference technical brief TB379 and AN9922 for additional
information on thermal characterization and board layout
considerations.
TABLE 2. ISL5585 3V APPLICATION CIRCUIT COMPONENTS
COMPONENT
VALUE
ISL5585
18.7k
23.7k
49.9k
71.5k
66.5k
30.1k
36.5k
42.2Kk
45.3k
0.47
μ
F
4.7
μ
F
0.1
μ
F
0.1
μ
F
1N400X type with breakdown > 100V.
TOL
N/A
1%
1%
1%
1%
1%
1%
1%
1%
1%
20%
20%
20%
20%
RATING
N/A
0.1W
0.1W
0.1W
0.1W
0.1W
0.1W
0.1W
0.1W
0.1W
10V
6.3V
>100V
100V
U1 - Ringing SLIC
R
TL
R
RT
R
SH
R
IL
R
S
R
F
R
A
R
B
R
IN
C
RS
, C
TX
, C
RT
, C
POL
C
DC
, C
FB
C
PS1
C
PS2
, C
PS3
D
1
R
P1
, R
P2
Standard applications will use
49
per side. Protection resistor
values are application dependent and will be determined by
protection requirements.
Design Parameters: Ring Trip Threshold = 76mA
PEAK
, Switch Hook
Threshold = 12mA, Loop Current Limit = 24.6mA, Synthesize Device
Impedance = (3*66.5k
)
/400 = 498.8
, with 49.9
protection
resistors, impedance across Tip and Ring terminals = 599
.
Transient current limit = 95mA.
FIGURE 17. ISL5585 3.3V APPLICATION CIRCUIT
AUX
VRS
AGND
TIP
VFB
BGND
RING
VTX
-IN
SH
RT
CDC
ILIM
ISL5585
V
CC
POL
C
RS
R
IL
C
FB
R
S
R
SH
C
RT
R
RT
C
POL
C
DC
U
1
R
P1
49.9
R
P2
49.9
VCC
VBL
VBH
D
1
1N4004
C
PS1
C
PS3
C
PS2
TL
R
TL
+
-
R
F
R
A
R
B
0dB
CODEC
+2.4V
TX IN
R
IN
V
2W
-
+
PCM to V
2W
Gain = +3.33dB, digital gain set to 0dB
V
2W
to PCM Gain = -9.3 dB, digital gain set to 0dB
0 dBm0, CODEC output voltage = 0.531Vrms
0 dBm0, V
2W
= 0.7795Vrms
Digital
0dB
Digital
PCM
PCM
Design Equations
R
S
= 133.33(Z
L
- 2R
P
)
Gain PCM to V
2W
= R
S
/R
IN
= 66.5k/45.3k =1.46
dB Gain =20log (0.7795/ 0.531) = +3.33dB
66.5k
45.3k
V
2W
to PCM Gain = V
2W
(G
2-4
)(R
F
/R
A
) = (0.7795)(0.416)(30.1k/36.5k) = 0.267
dB Gain =20log (0.267/0.7795) = - 9.3dB
30.1k
36.5k
42.2k
0.47uF
0.47uF
0.47uF
600
ISL5585
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