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參數(shù)資料
| 型號： | ISL55143 |
| 廠商： | Intersil Corporation |
| 英文描述： | High-Speed 18V CMOS Comparators(高速18V CMOS比較器) |
| 中文描述： | 高速18V的CMOS比較器（高速18V的的CMOS比較器） |
| 文件頁數(shù)： | 14/14頁 |
| 文件大?。?/td> | 370K |
| 代理商： | ISL55143 |
14
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6230.0
July 17, 2006
Thin Quad Flat No-Lead Plastic Package (TQFN)
INDEX
AREA
D/2
D
E/2
E
A
B
C
0.10
B
A
M C
A
N
SEATING PLANE
N
6
3
2
1
2
3
e
1
0.08
SECTION "C-C"
NX b
A1
2X
C
0.15
0.15
2X
B
REF.
(Nd-1)Xe
(Ne-1)Xe
REF.
5
A1
A
C
C
A3
D2
D2
2
E2
E2/2
SIDE VIEW
TOP VIEW
7
BOTTOM VIEW
7
5
NX k
NX b
8
NX L
8
8
0.10 C
/ /
(DATUM B)
(DATUM A)
INDEX
AREA
6
N
L36.6x6
36 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220WJJD-1 ISSUE C)
SYMBOL
MILLIMETERS
NOTES
MIN
NOMINAL
MAX
A
0.70
0.75
0.80
-
A1
-
-
0.05
-
A3
0.20 REF
b
0.18
0.25
0.30
5, 8
D
6.00 BSC
-
D2
3.80
3.95
4.05
7, 8
E
6.00 BSC
-
E2
3.80
3.95
4.05
7, 8
e
0.50 BSC
-
k
0.20
-
-
-
L
0.45
0.55
0.65
8
N
36
2
Nd
9
3
Ne
9
3
Rev. 2 04/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
ISL55141, ISL55142, ISL55143
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相關(guān)代理商/技術(shù)參數(shù) |
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| ISL55143IRZ | 功能描述:IC COMP CMOS HS 18V 36-TQFN RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:通用 元件數(shù):1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標(biāo)準(zhǔn)）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標(biāo)準(zhǔn)）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
| ISL55143IRZEVAL1Z | 功能描述:EVALUATION BOARD FOR ISL55143IRZ RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:* 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| ISL55143IRZ-T | 功能描述:IC COMP CMOS HS 18V 36-TQFN RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:通用 元件數(shù):1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標(biāo)準(zhǔn)）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標(biāo)準(zhǔn)）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
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