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參數(shù)資料
| 型號(hào)： | ISL54103 |
| 廠商： | Intersil Corporation |
| 英文描述： | DDC Accelerator (DDCA)(DDC加速器(DDCA)) |
| 中文描述： | DDC的加速器（DDCA）（DDC的加速器（DDCA）） |
| 文件頁數(shù)： | 5/7頁 |
| 文件大小： | 177K |
| 代理商： | ISL54103 |
5
FN6303.1
June 22, 2006
Functional Description
DDC Overview
DDC is a 2-wire serial communication standard based on the
I
2
C standard. Devices communicate to each other using one
clock (SCL) and one data (SDA) line. These are both
bidirectional.
Each signal is connected to a positive supply voltage via a
current-source or pull-up resistor (see “System Diagram” on
page 2). When the bus is free, both lines are HIGH. The
output stages of all devices connected to the bus must have
an open-drain or open-collector to perform the wired-AND
function.
Simple pull-up resistors on the clock and data lines work well
unless there are long signal lines. The combined
capacitance of long cables increases the rise time on the
signal to such an extent that the communication becomes
unreliable or fails to meet the bus timing specifications.
Smaller value resistors can sometimes compensate for the
extra capacitance, but this increases the current
consumption when the signal lines are pulled LOW.
ISL54103 Operation
To improve the operation of the DDC where larger bus
capacitance exists, the ISL54103 provides active pull-up
using switched current sources. When the bus is idle and
both lines are HIGH, a standby pull-up current of 100μA is
used to maintain the signal level while minimizing power
FIGURE 5. V
TRIPH
VOLTAGE
FIGURE 6. I
DD
CURRENT, DDC1 = DDC2 = OPEN
FIGURE 7. BOOST PULL-UP CURRENT vs DDC VOLTAGE
Typical Performance Curves
(Continued)
0.50
0.55
0.60
0.65
0.70
0.45
0.40
0.35
0.30
-40
-20
0
20
40
60
80
100
-60
TEMPERATURE (°C)
I
T
D
-
VDD = 5.5V
VDD = 2.7V
75
80
85
90
95
70
65
60
55
-40
-20
0
20
40
60
80
100
-60
TEMPERATURE (°C)
S
D
VDD = 5.5V
VDD = 2.7V
2.0
2.5
3.0
3.5
1.5
1.0
0.5
0
1
2
3
4
5
0
DDC VOLTAGE (V)
B
O
6
VDD = 5.0V
VDD = 2.7V
ISL54103
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