參數(shù)資料
型號: ISL54056IRUZ-T
廠商: INTERSIL CORP
元件分類: 運動控制電子
英文描述: Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Quad SPDT (Dual DPDT) Analog Switch
中文描述: QUAD 1-CHANNEL, SGL POLE DOUBLE THROW SWITCH, PQCC16
封裝: 2.60 X 1.80 MM, 0.50 MM HEIGHT, 0.40 MM PITCH, ROHS COMPLIANT, PLASTIC, MO-255, UTQFN-16
文件頁數(shù): 12/12頁
文件大?。?/td> 274K
代理商: ISL54056IRUZ-T
12
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6357.1
October 30, 2006
ISL54056
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
6
B
E
A
D
0.10 C
2X
C
0.05 C
A
0.10 C
A1
SEATING PLANE
INDEX AREA
2
1
N
TOP VIEW
BOTTOM VIEW
SIDE VIEW
NX (b)
SECTION "C-C"
e
C C
5
C
TERMINAL TIP
(A1)
L
0.10 C
2X
e
L1
NX L
2
1
0.10 M C A B
0.05 M C
5
NX b
16X
(DATUM B)
(DATUM A)
PIN #1 ID
3.00
1.80
1.40
2.20
0.40
0.50
0.20
0.40
0.20
0.90
1.40
LAND PATTERN
10
L16.2.6x1.8A
16 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
SYMBOL
MILLIMETERS
NOTES
MIN
NOMINAL
MAX
A
0.45
0.50
0.55
-
A1
-
-
0.05
-
A3
0.127 REF
-
b
0.15
0.20
0.25
5
D
2.55
2.60
2.65
-
E
1.75
1.80
1.85
-
e
0.40 BSC
-
L
0.35
0.40
0.45
-
L1
0.45
0.50
0.55
-
N
16
2
Nd
4
3
Ne
4
3
θ
0
-
12
4
Rev. 4 8/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. JEDEC Reference MO-255.
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
相關PDF資料
PDF描述
ISL54056 Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Quad SPDT (Dual DPDT) Analog Switch(超低導通電阻, +1.65V到+4.5V, 單電源, 四路單刀雙擲(雙路單刀雙擲)模擬開關)
ISL54057IRUZ-T Ultra Low ON-Resistance, Low-Voltage, Single Supply, Differential 4 to 1 Analog Multiplexer
ISL54057 Ultra Low ON-Resistance, Low-Voltage, Single Supply, Differential 4 to 1 Analog Multiplexer(超低導通電阻, 低電壓, 單電源, 差分4合1模擬開關)
ISL54058IRUZ-T Ultra Low ON-Resistance, Low-Voltage, Single Supply, Dual 4 to 1 Analog Multiplexer
ISL54058 Ultra Low ON-Resistance, Low-Voltage, Single Supply, Dual 4 to 1 Analog Multiplexer(超低導通電阻, 低電壓, 單電源, 雙路4合1模擬開關)
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