參數(shù)資料
型號: ISL5239KI
廠商: INTERSIL CORP
元件分類: 消費家電
英文描述: Pre-Distortion Linearizer
中文描述: SPECIALTY CONSUMER CIRCUIT, PBGA196
封裝: 15 X 15 MM, PLASTIC, BGA-196
文件頁數(shù): 17/31頁
文件大?。?/td> 653K
代理商: ISL5239KI
17
Hold Time SERIN from CLK (Note 7)
t
DHS
1
ns
Delay Time from CLK to TRIGOUT
t
PDC
2 (Note 7)
7
ns
Setup Time from TRIGIN to CLK
t
DS1
2
ns
Hold Time TRIGIN from CLK
t
DH1
2
ns
Setup Time from TMS and TDI to TCK
t
TS
3
ns
Hold Time TMS and TDI from TCK
t
TH
3
ns
Delay Time from TCK to TDO valid
t
TD
8
ns
Test Clock Frequency
f
T
50
MHz
Output Rise/Fall Time (Note 7)
t
RF
-
3
ns
NOTES:
6. AC tests performed with C
L
= 70pF. Input reference level for CLK is 1.5V, all other inputs 1.5V.
Test V
IH
= 3.0V, V
IHC
= 3.0V, V
IL
= 0V, V
OL
= 1.5V, V
OH
= 1.5V.
7. Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes.
8. Can be asynchronous to CLK, specification guarantying which CLK edge the device comes out of reset on.
9. Can be asynchronous to CLK, specification guarantying which CLK edge the device begins the read cycle on.
AC Electrical Specifications
V
CCC
= 1.8± 5%, V
CCIO
= 3.3 ± 5%, T
A
= -40
o
C to 85
o
C (Note 6)
(Continued)
PARAMETER
SYMBOL
MIN
MAX
UNITS
AC Test Load Circuit
EQUIVALENT CIRCUIT
C
L
I
OH
1.5V
I
OL
DUT
SWITCH S
1
OPEN FOR I
CCSB
AND I
CCOP
S
1
±
TEST HEAD CAPACITANCE
Waveforms
FIGURE 15. CLOCK AND RESET TIMING
FIGURE 16. SERIAL INTERFACE RELATIVE TIMING
CLK
t
RS
t
RPW
RESET
t
CH
t
CL
t
CLK
t
CLK
= 1 / F
CLK
t
RH
CLK
SERCLK
SERSYNC
SEROUT
t
SC1,
t
SCN
t
SD1
t
SD2
SERIN
t
DSS
t
DHS
ISL5239
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