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參數(shù)資料
| 型號： | ISL45041IRZ-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VCOM CALIBRATOR TFT/LCD 8TDFN |
| 標(biāo)準(zhǔn)包裝： | 6,000 |
| 類型： | 校準(zhǔn)器 |
| 應(yīng)用： | LCD 顯示器 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-WDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 8-TDFN（3x3） |
| 包裝： | 帶卷 (TR) |
5
FN6189.4
December 17, 2010
Application Information
This device provides the ability to reduce the flicker of an LCD
panel by adjustment of the VCOM voltage during production
test and alignment. A 128-step resolution is provided under
digital control, which adjusts the sink current of the output.
The output is connected to an external voltage divider, so that
the device will have the capability to reduce the voltage on the
output by increasing the output sink current.
The adjustment of the output is provided by the 2-wire I2C
serial interface.
Expected Output Voltage
The ISL45041 provides an output sink current, which lowers
the voltage on the external voltage divider (VCOM output
the output current (IOUT) and output voltage (VOUT) values.
The setting is the register value +1 with a value between 1
and 128.
values of: RSET = 24.9kΩ, R1 = 200kΩ, R2 = 243kΩ, and
AVDD =10V.
RSET Resistor
The external RSET resistor sets the full-scale sink current, ISET
maximum, that determines the lowest voltage of the external
between the OUT pin and SET pin (Figure 2), which are also
the drain and source of the output transistor, must be greater
than 1.75V. This will keep the output transistor in its saturation
region to maintain linear operation over the full range of register
values. Expected current settings and 7-bit accuracy occurs
when the output MOS transistor is operating in the saturation
region. Figure 2 shows the internal connection for the output
MOS transistor. The value of the AVDD supply sets the voltage
at the source of the output transistor. This voltage is equal to
(Setting/128) x (AVDD/20). The ISET current is therefore equal
to (Setting/128) x (AVDD/20 x RSET). The drain voltage is
(setting equal to 128) so the minimum value of VOUT is greater
than 1.75V + AVDD/20.
Ramp-Up of the VDD Power Supply
The ramp-up from 10% VDD to 90% VDD level must be
achieved in 10ms or less to ensure that the EEPROM and
power-on-reset circuits are synchronized and the correct
value is read from the EEPROM Memory.
Power Supply Sequence
The recommended power supply sequencing is shown in
Figure 3. When applying power, VDD should be applied
before or at the same time as AVDD. The minimum time for
tVS is 0s. When removing power, the sequence of VDD and
AVDD is not important.
Do not remove VDD or AVDD within 100ms of the start of the
EEPROM programming cycle. Removing power before the
EEPROM programming cycle is completed may result in
corrupted data in the EEPROM.
TABLE 1.
SETTING VALUE
VOUT
1
5.486
10
5.313
20
5.141
30
4.969
40
4.797
50
4.625
60
4.453
70
4.281
80
4.109
90
3.936
100
3.764
110
3.592
128
3.282
RSET
FIGURE 1. OUTPUT CONNECTION CIRCUIT EXAMPLE
-
+
ISL45041
SET
OUT
AVDD
R1
R2
AVDD
IOUT
IOUT
Setting
128
---------------------
x
AVDD
20 RSET
()
---------------------------
=
VOUT
R2
R1 R2
+
---------------------
AVDD 1
Setting
128
---------------------
x
R1
20 RSET
()
---------------------------
–
=
(EQ. 1)
(EQ. 2)
FIGURE 2. OUTPUT CONNECTION CIRCUIT EXAMPLE
AVDD = 15V
RSET
OUT PIN
R1
R2
AVDD
VSAT
SET PIN
SETTING
128
----------------------------x
AVDD
20
------------------
0.5V
FIGURE 3. POWER SUPPLY SEQUENCE
VDD
AVDD
tVS
ISL45041
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL45042 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:LCD Module Calibrator |
| ISL45042_06 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:LCD Module Calibrator |
| ISL45042_07 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:LCD Module Calibrator |
| ISL45042_11 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:LCD Module Calibrator |
| ISL45042A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:LCD Module Calibrator |
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