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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | ISL43L840IV-T |
| 寤犲晢锛� | Intersil |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 9/11闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MUX/DEMUX DUAL 4X1 16TSSOP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 2,500 |
| 鍔熻兘锛� | 澶氳矾寰�(f霉)鐢ㄥ櫒/澶氳矾鍒嗚В鍣� |
| 闆昏矾锛� | 2 x 4:1 |
| 灏�(d菐o)閫氱媭鎱�(t脿i)闆婚樆锛� | 750 姣瓙 |
| 闆诲闆绘簮锛� | 鍠浕婧� |
| 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� | 1.6 V ~ 3.6 V |
| 闆绘祦 - 闆绘簮锛� | 50nA |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 16-TSSOP锛�0.173"锛�4.40mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 16-TSSOP |
| 鍖呰锛� | 甯跺嵎 (TR) |
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)鐣�(d膩ng)鍓嶇9闋�(y猫)绗�10闋�(y猫)绗�11闋�(y猫)
7
FN6096.1
reduced and the resistance may increase, especially at low
supply voltages.
Power-Supply Considerations
The ISL43L840 construction is typical of most CMOS analog
switches, in that they have two supply pins: V+ and GND. V+
and GND drive the internal CMOS switches and set their
analog voltage limits. Unlike switches with a 4V maximum
supply voltage, the ISL43L840 4.7V maximum supply
voltage provides plenty of room for the 10% tolerance of
3.6V supplies, as well as room for overshoot and noise
spikes.
The minimum recommended supply voltage is 1.6V but the
part will operate with a supply below 1.5V. It is important to
note that the input signal range, switching times, and on-
resistance degrade at lower supply voltages. Refer to the
electrical specification tables and Typical Performance
curves for details.
V+ and GND power the internal logic (thus setting the digital
switching point) and level shifters. The level shifters convert
the logic levels to switched V+ and V- signals to drive the
analog switch gate terminals.
Logic-Level Thresholds
The device is 1.8V CMOS compatible (0.5V and 1.4V) over a
supply range of 2.0V to 3.6V (see Figure 13). At 3.6V the VIH
level is about 1.27V. This is still below the 1.8V CMOS
guaranteed high output minimum level of 1.4V, but noise
margin is reduced.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
High-Frequency Performance
In 50
systems, signal response is reasonably flat even past
10MHz with a -3dB bandwidth of 70MHz (see Figure 15).
The frequency response is very consistent over a wide V+
range, and for varying analog signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal feed
through from a switch鈥檚 input to its output. Off Isolation is the
resistance to this feed-through, while Crosstalk indicates the
amount of feed-through from one switch to another.
Figure 16 details the high Off Isolation and Crosstalk
rejection provided by this family. At 100kHz, Off Isolation is
about 65dB in 50
systems, decreasing approximately 20dB
per decade as frequency increases. Higher load
impedances decrease Off Isolation and Crosstalk rejection
due to the voltage divider action of the switch OFF
impedance and the load impedance.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND.
One of these diodes conducts if any analog signal exceeds
V+ or GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analog-
signal-path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and V+ or GND.
FIGURE 8. OVERVOLTAGE PROTECTION
GND
VCOM
VNOx
OPTIONAL PROTECTION
V+
DIODE
OPTIONAL PROTECTION
DIODE
OPTIONAL
PROTECTION
RESISTOR
FOR LOGIC
INPUTS
ADDX
1k
ISL43L840
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| ISL43L841IRZ-T | IC MUX/DEMUX 4X1 16TQFN |
| ISL4485EIB-T | IC TXRX 1TX/1RX 5V RS-485 8-SOIC |
| ISL4491EIB-T | IC TXRX RS-485/422 LP HS 14-SOIC |
| ISL5123IH-T | IC SWITCH SPDT SOT23-6 |
| ISL54047IRUZ-T | IC MUX/DEMUX 4X1 10UTQFN |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| ISL43L840IVZ | 鍔熻兘鎻忚堪:IC MUX/DEMUX DUAL 4X1 16TSSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鎺ュ彛 - 妯℃摤闁嬮棞(gu膩n)锛屽璺京(f霉)鐢ㄥ櫒锛屽璺垎瑙ｅ櫒 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:36 绯诲垪:- 鍔熻兘:澶氳矾寰�(f霉)鐢ㄥ櫒 闆昏矾:2 x 4:1 灏�(d菐o)閫氱媭鎱�(t脿i)闆婚樆:75 姝愬 闆诲闆绘簮:鍠�/闆欓浕婧� 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±):2 V ~ 12 V锛�±2 V ~ 6 V 闆绘祦 - 闆绘簮:- 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:20-SOIC锛�0.295"锛�7.50mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:20-SOIC W 鍖呰:绠′欢 |
| ISL43L840IVZ-T | 鍔熻兘鎻忚堪:IC MUX/DEMUX DUAL 4X1 16TSSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鎺ュ彛 - 妯℃摤闁嬮棞(gu膩n)锛屽璺京(f霉)鐢ㄥ櫒锛屽璺垎瑙ｅ櫒 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:36 绯诲垪:- 鍔熻兘:澶氳矾寰�(f霉)鐢ㄥ櫒 闆昏矾:2 x 4:1 灏�(d菐o)閫氱媭鎱�(t脿i)闆婚樆:75 姝愬 闆诲闆绘簮:鍠�/闆欓浕婧� 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±):2 V ~ 12 V锛�±2 V ~ 6 V 闆绘祦 - 闆绘簮:- 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:20-SOIC锛�0.295"锛�7.50mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:20-SOIC W 鍖呰:绠′欢 |
| ISL43L841 | 鍒堕€犲晢:INTERSIL 鍒堕€犲晢鍏ㄧū:Intersil Corporation 鍔熻兘鎻忚堪:Ultra Low ON-Resistance, Low-Voltage, Single Supply, Differential 4 to 1 Analog Multiplexer |
| ISL43L841IRZ | 鍔熻兘鎻忚堪:IC MUX/DEMUX 4X1 16TQFN RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鎺ュ彛 - 妯℃摤闁嬮棞(gu膩n)锛屽璺京(f霉)鐢ㄥ櫒锛屽璺垎瑙ｅ櫒 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:36 绯诲垪:- 鍔熻兘:澶氳矾寰�(f霉)鐢ㄥ櫒 闆昏矾:2 x 4:1 灏�(d菐o)閫氱媭鎱�(t脿i)闆婚樆:75 姝愬 闆诲闆绘簮:鍠�/闆欓浕婧� 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±):2 V ~ 12 V锛�±2 V ~ 6 V 闆绘祦 - 闆绘簮:- 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:20-SOIC锛�0.295"锛�7.50mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:20-SOIC W 鍖呰:绠′欢 |
| ISL43L841IRZ-T | 鍔熻兘鎻忚堪:IC MUX/DEMUX 4X1 16TQFN RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鎺ュ彛 - 妯℃摤闁嬮棞(gu膩n)锛屽璺京(f霉)鐢ㄥ櫒锛屽璺垎瑙ｅ櫒 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:36 绯诲垪:- 鍔熻兘:澶氳矾寰�(f霉)鐢ㄥ櫒 闆昏矾:2 x 4:1 灏�(d菐o)閫氱媭鎱�(t脿i)闆婚樆:75 姝愬 闆诲闆绘簮:鍠�/闆欓浕婧� 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±):2 V ~ 12 V锛�±2 V ~ 6 V 闆绘祦 - 闆绘簮:- 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:20-SOIC锛�0.295"锛�7.50mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:20-SOIC W 鍖呰:绠′欢 |
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