參數(shù)資料
型號(hào): ISL4243EIRZ-T
廠商: INTERSIL CORP
元件分類: 通用總線功能
英文描述: QFN Packaged, +/-15kV ESD Protected, +2.7V to +5.5V, 10Nanoamp, 250kbps, RS-232 Transmitters/Receivers
中文描述: TRIPLE LINE TRANSCEIVER, PQCC32
封裝: 5 X 5 MM, LEAD FREE, PLASTIC, QFN-32
文件頁(yè)數(shù): 11/13頁(yè)
文件大?。?/td> 377K
代理商: ISL4243EIRZ-T
11
Interconnection with 3V and 5V Logic
The ISL424XE directly interface with 5V CMOS and TTL
logic families. Nevertheless, with the ISL424XE at 3.3V, and
the logic supply at 5V, AC, HC, and CD4000 outputs can
drive ISL424XE inputs, but ISL424XE outputs do not reach
the minimum V
IH
for these logic families. See Table 3 for
more information.
±
15kV ESD Protection
All pins on ISL424XE devices include ESD protection
structures, but the RS-232 pins (transmitter outputs and
receiver inputs) incorporate advanced structures which allow
them to survive ESD events up to
±
15kV. The RS-232 pins
are particularly vulnerable to ESD damage because they
typically connect to an exposed port on the exterior of the
finished product. Simply touching the port pins, or
connecting a cable, can cause an ESD event that might
destroy unprotected ICs. These new ESD structures protect
the device whether or not it is powered up, protect without
allowing any latchup mechanism to activate, and don’t
interfere with RS-232 signals as large as
±
25V.
Human Body Model (HBM) Testing
As the name implies, this test method emulates the ESD
event delivered to an IC during human handling. The tester
delivers the charge through a 1.5k
current limiting resistor,
making the test less severe than the IEC61000 test which
utilizes a 330
limiting resistor. The HBM method
determines an ICs ability to withstand the ESD transients
typically present during handling and manufacturing. Due to
the random nature of these events, each pin is tested with
respect to all other pins. The RS-232 pins on “E” family
devices can withstand HBM ESD events to
±
15kV.
IEC61000-4-2 Testing
The IEC61000 test method applies to finished equipment,
rather than to an individual IC. Therefore, the pins most likely
to suffer an ESD event are those that are exposed to the
outside world (the RS-232 pins in this case), and the IC is
tested in its typical application configuration (power applied)
rather than testing each pin-to-pin combination. The lower
current limiting resistor coupled with the larger charge
FIGURE 9. TRANSMITTER LOOPBACK TEST CIRCUIT
FIGURE 10. LOOPBACK TEST AT 120kbps
FIGURE 11. LOOPBACK TEST AT 250kbps
ISL424XE
V
CC
FORCEOFF or SHDN
C
1
C
2
C
4
+
C
3
+
+
+
1000pF
V+
V-
5k
T
IN
R
OUT
C1+
C1-
C2+
C2-
R
IN
T
OUT
+
V
CC
0.1
μ
F
V
CC
FORCEON
T1
IN
T1
OUT
R1
OUT
5
μ
s/DIV.
V
CC
= +3.3V
C1 - C4 = 0.1
μ
F
5V/DIV.
T1
IN
T1
OUT
R1
OUT
2
μ
s/DIV.
5V/DIV.
V
CC
= +3.3V
C1 - C4 = 0.1
μ
F
TABLE 3. LOGIC FAMILY COMPATIBILITY WITH VARIOUS
SUPPLY VOLTAGES
SYSTEM
POWER-SUPPLY
VOLTAGE
(V)
V
CC
SUPPLY
VOLTAGE
(V)
COMPATIBILITY
3.3
3.3
Compatible with all CMOS
families.
5
5
Compatible with all TTL and
CMOS logic families.
5
3.3
Compatible with ACT and HCT
CMOS, and with TTL. ISL424XE
outputs are incompatible with AC,
HC, and CD4000 CMOS inputs.
ISL4241E, ISL4243E
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