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參數(shù)資料
| 型號(hào)： | ISL3874 |
| 廠商： | Intersil Corporation |
| 元件分類： | 基帶處理器 |
| 英文描述： | Wireless LAN Integrated Medium Access Controller with Baseband Processor with Mini-PCI |
| 中文描述： | 集成的無線局域網(wǎng)媒體訪問控制器的基帶微型處理器的PCI |
| 文件頁數(shù)： | 7/33頁 |
| 文件大小： | 390K |
| 代理商： | ISL3874 |
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TABLE 4. SERIAL EEPROM PORT CONNECTIONS
PIN NAME
PIN NUMBER
PIN I/O TYPE
DESCRIPTION
PJ0
P5
CMOS BiDir, 2mA, 50K Pull Up
SCLK, serial clock for serial EEPROM devices
PJ1
T1
CMOS BiDir, 2mA, 50K Pull Down
Serial Data Out (SD) used on serial EEPROM devices which require
three and four wire interfaces, example: AT45DB011
PJ2
R3
CMOS BiDir, 2mA, 50K Pull Down
Serial Data In (MISO) used on serial EEPROM devices, Used in four wire
serial devices only. Not currently supported in software. Consult the
factory for additional updates on this option.
TCLKIN(CS)
L4
I/O, 50K Pull Down
CS used for Chip Select Output for Serial Devices which have a 4 wire
interface like the AST45DB011 and also serial data on two wire devices
like the 24C08.
TABLE 5. CLOCKS PORT PINS
PIN NAME
PIN NUMBER
PIN I/O TYPE
DESCRIPTION
XTALIN
J2
Analog Input
32.768kHz Crystal Input
XTALOUT
J1
CMOS Output, 2mA
32.768kHz Crystal Output
CLKOUT
A2
CMOS, TS Output, 2mA
Clock Output (Selectable as MCLK, TCLK, or TOUT0)
BBP_CLK
J16
Input
Baseband Processor Clock. The nominal frequency for this clock is 44 MHz.
TABLE 6. BASEBAND PROCESSOR RECEIVER PORT PINS
PIN NAME
PIN NUMBER PIN I/O TYPE
DESCRIPTION
RX_IF_AGC
T16
O
Analog drive to the IF AGC control.
RX_RF_AGC
P16
O
Drive to the RF AGC stage attenuator. CMOS digital.
RX_IF_DET
R10
I
Analog input to the receive power A/D converter for AGC control.
RXI+
R7
I
Analog input to the internal 6-bit A/D of the In-phase received data. Balanced differential.
RXI-
T7
I
Analog input to the internal 6-bit A/D of the In-phase received data. Balanced differential.
RXQ+
R9
I
Analog input to the internal 6-bit A/D of the Quadrature received data. Balanced differential.
RXQ-
T9
I
Analog input to the internal 6-bit A/D of the Quadrature received data. Balanced differential.
TABLE 7. BASEBAND PROCESSOR TRANSMITTER PORT PINS
PIN NAME
PIN NUMBER PIN I/O TYPE
DESCRIPTION
TX_AGC_IN
T10
I
Input to the transmit power A/D converter for transmit AGC control.
TX_IF_AGC
R16
O
Analog drive to the transmit IF power control.
TXI+
R12
O
TX Spread baseband I digital output data. Data is output at the chip rate. Balanced differential.
TXI
T12
O
TX Spread baseband I digital output data. Data is output at the chip rate. Balanced differentia.
TXQ
+
R14
O
TX Spread baseband Q digital output data. Data is output at the chip rate. Balanced differential.
TXQ
T14
O
TX Spread baseband Q digital output data. Data is output at the chip rate. Balanced differential.
ISL3874
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