7 FN6965.1 March 25, 2010 Operation The ISL36411 is an advanced quad lane-extender for high-speed interconnects. A functional diagram " />
參數(shù)資料
型號(hào): ISL36411DRZ-T7
廠商: Intersil
文件頁(yè)數(shù): 10/12頁(yè)
文件大?。?/td> 0K
描述: IC EQUALIZER REC 11.3GBPS 46QFN
標(biāo)準(zhǔn)包裝: 1
系列: QLx™
應(yīng)用: 數(shù)據(jù)傳輸
電源電壓: 1.1 V ~ 1.3 V
封裝/外殼: 46-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 46-TQFN
包裝: 標(biāo)準(zhǔn)包裝
安裝類(lèi)型: 表面貼裝
其它名稱(chēng): ISL36411DRZ-T7-DKR-ND
ISL36411DRZ-T7DKR
ISL36411DRZ-TS-DKR
ISL36411DRZ-TS-DKR-ND
QLX411RIQT7-DKR
QLX411RIQT7-DKR-ND
ISL36411
7
FN6965.1
March 25, 2010
Operation
The ISL36411 is an advanced quad lane-extender for
high-speed interconnects. A functional diagram of one of
the four channels in the ISL36411 is shown in Figure 3.
In addition to a robust equalization filter to compensate
for channel loss and restore signal fidelity, the ISL36411
contains unique integrated features to preserve special
signaling protocols typically broken by other equalizers.
The signal detect function is used to mute the channel
output when the equalized signal falls below the level
determined by the Detection Threshold (DT) pin voltage.
This function is intended to preserve periods of line
silence (“quiescent state” in InfiniBand contexts).
Furthermore, the output of the signal detect / DT
comparator is used as a loss of signal (LOS) indicator to
indicate the absence of a received signal.
As illustrated in Figure 3, the core of each high-speed
signal path in the ISL36411 is a sophisticated equalizer
followed by a limiting amplifier. The equalizer
compensates for skin loss, dielectric loss, and impedance
discontinuities in the transmission channel. Each
equalizer is followed by a limiting amplification stage that
provides a clean output signal with full amplitude swing
and fast rise-fall times for reliable signal decoding in a
subsequent receiver.
Adjustable Equalization Boost
Each channel in the ISL36411 features a settable (in
pairs) equalizer for custom signal restoration. The
flexibility of this adjustable compensation architecture
enables signal fidelity to be optimized on a
channel-by-channel basis, providing support for a wide
variety of channel characteristics and data rates ranging
from 2.5Gbps to 11.1Gbps. Because the boost level is
externally set rather than internally adapted, the
ISL36411 provides reliable communication from the very
first bit transmitted. There is no time needed for
adaptation and control loop convergence. Furthermore,
there are no pathological data pat-terns that will cause
the ISL36411 to move to an incorrect boost level.
Control Pin Boost Setting
The connectivity of the CP pins is used to determine the
boost level of each pair of channels. CP1 controls the
boost of channels 1 and 2, CP2 controls the boosts of
channels 3 and 4. Table 1 defines the mapping from the
2-bit CP word to the 8 possible boost levels.
FIGURE 3. FUNCTIONAL DIAGRAM OF A SINGLE CHANNEL WITHIN THE ISL36411
Signal
Detector
IN[P]
IN[N]
DT
LOSB
OUT[N]
OUT[P]
Adjustable
Equalizer
CP
A
CP
B
Limiting
Amplifier
Output
Driver
TABLE 1. MAPPING BETWEEN BOOST LEVEL AND
CP-PIN CONNECTIVITY
CPA
CPB
BOOST LEVEL
Float
0
Float
GND
1
GND
VDD
2
Float
VDD
3
VDD
Float
4
GND
Float
5
GND
6
VDD
GND
7
VDD
8
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