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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | ISL28210FBZ-T7 |
| 寤犲晢锛� | Intersil |
| 鏂囦欢闋佹暩(sh霉)锛� | 8/23闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC OPAMP JFET 12.5MHZ DUAL 8SOIC |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Solutions for Industrial Control Applications |
| 妯欐簴鍖呰锛� | 1,000 |
| 鏀惧ぇ鍣ㄩ鍨嬶細 | J-FET |
| 闆昏矾鏁�(sh霉)锛� | 2 |
| 杞�(zhu菐n)鎻涢€熺巼锛� | 20 V/µs |
| 澧炵泭甯跺绌嶏細 | 12.5MHz |
| 闆绘祦 - 杓稿叆鍋忓锛� | 2pA |
| 闆诲 - 杓稿叆鍋忕Щ锛� | 300µV |
| 闆绘祦 - 闆绘簮锛� | 2.55mA |
| 闆绘祦 - 杓稿嚭 / 閫氶亾锛� | 50mA |
| 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� | 9 V ~ 40 V锛�±4.5 V ~ 20 V |
| 宸ヤ綔婧害锛� | -40°C ~ 125°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 8-SOIC锛�0.154"锛�3.90mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 8-SOIC |
| 鍖呰锛� | 甯跺嵎 (TR) |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�鐣�(d膩ng)鍓嶇8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�
ISL28110, ISL28210
16
FN6639.3
November 29, 2012
Power Dissipation
It is possible to exceed the +150掳C maximum junction
temperatures under certain load and power supply conditions. It
is therefore important to calculate the maximum junction
temperature (TJMAX) for all applications to determine if power
supply voltages, load conditions, or package type need to be
modified to remain in the safe operating area. These parameters
are related using Equation 1:
where:
PDMAXTOTAL is the sum of the maximum power dissipation of
each amplifier in the package (PDMAX)
where:
TMAX = Maximum ambient temperature
胃JA = Thermal resistance of the package
PDMAX = Maximum power dissipation of 1 amplifier
VS = Total supply voltage
IqMAX = Maximum quiescent supply current of 1 amplifier
VOUTMAX = Maximum output voltage swing of the application
RL = Load resistance
ISL28110 and ISL28210 SPICE Model
the net list for the SPICE model. The model is a simplified version
of the actual device and simulates important AC and DC
parameters. AC parameters incorporated into the model are: 1/f
and flatband noise voltage, Slew Rate, CMRR, Gain and Phase. The
DC parameters are IOS, total supply current and output voltage
swing. The model uses typical parameters given in the 鈥淓lectrical
Specifications鈥� Table beginning on page 4. The AVOL is adjusted
for 125dB with the dominant pole at 7Hz. The CMRR is set 120dB,
f = 280kHz. The input stage models the actual device to present
an accurate AC representation. The model is configured for
ambient temperature of +25掳C.
results for the Noise Voltage, Closed Loop Gain vs Frequency,
Small Signal 0.1V Step, Large Signal 5V Step Response, Open
Loop Gain Phase, CMRR and Output Voltage Swing for 卤5V and
卤15V supplies.
LICENSE STATEMENT
The information in this SPICE model is protected under the
United States copyright laws. Intersil Corporation hereby grants
users of this macro-model hereto referred to as 鈥淟icensee鈥�, a
nonexclusive, nontransferable licence to use this model as long
as the Licensee abides by the terms of this agreement. Before
using this macro-model, the Licensee should read this license. If
the Licensee does not accept these terms, permission to use the
model is not granted.
The Licensee may not sell, loan, rent, or license the macro-model,
in whole, in part, or in modified form, to anyone outside the
Licensee鈥檚 company. The Licensee may modify the macro-model
to suit his/her specific applications, and the Licensee may make
copies of this macro-model for use within their company only.
This macro-model is provided 鈥淎S IS, WHERE IS, AND WITH NO
WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED,
INCLUDING BUY NOT LIMITED TO ANY IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.鈥�
In no event will Intersil be liable for special, collateral, incidental,
or consequential damages in connection with or arising out of
the use of this macro-model. Intersil reserves the right to make
changes to the product and the macro-model without prior
notice.
FIGURE 45. UNITY-GAIN THD+N vs OUTPUT VOLTAGE vs
TEMPERATURE AT VS = 卤5V FOR 600惟 LOAD
0.0001
0.001
0.01
0.1
1
0
1
2
345
67
8
9
10
VP-P (V)
THD+N
(%)
VS = 卤5V
RL = 600惟
AV = 1
+25掳C
0掳C
-40掳C
+125掳C
+85掳C
TJMAX
TMAX 胃JAxPDMAXTOTAL
+
=
(EQ. 1)
PDMAX
VS IqMAX VS
(
- VOUTMAX)
VOUTMAX
RL
----------------------------
脳
+
脳
=
(EQ. 2)
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| 598456015000003 | CONNECTOR FEMALE 15POS SOLDER |
| 5-160491-1 | CONN UNINS RECPT 13-17AWG 0.187 |
| 208477160012049 | CONNECTOR RECEPT 160POS R/A |
| 62443-2 | CONN UNINS TAB 10-12AWG 0.187 |
| 928794-3 | CONN UNINS TAB 13-17AWG 0.110 |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| ISL28210FBZ-T7A | 鍔熻兘鎻忚堪:IC OPAMP JFET 12.5MHZ DUAL 8SOIC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> Linear - Amplifiers - Instrumentation 绯诲垪:- 妯欐簴鍖呰:2,500 绯诲垪:- 鏀惧ぇ鍣ㄩ鍨�:閫氱敤 闆昏矾鏁�(sh霉):2 杓稿嚭椤炲瀷:婊挎摵骞� 杞�(zhu菐n)鎻涢€熺巼:350 V/µs 澧炵泭甯跺绌�:180MHz -3db甯跺:320MHz 闆绘祦 - 杓稿叆鍋忓:12.5µA 闆诲 - 杓稿叆鍋忕Щ:800µV 闆绘祦 - 闆绘簮:15mA 闆绘祦 - 杓稿嚭 / 閫氶亾:85mA 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±):2.5 V ~ 12.6 V锛�±1.25 V ~ 6.3 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-TSSOP锛�8-MSOP锛�0.118"锛�3.00mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:8-MSOP 鍖呰:甯跺嵎 (TR) |
| ISL28210FRTBZ | 鍒堕€犲晢:INTERSIL 鍒堕€犲晢鍏ㄧū:Intersil Corporation 鍔熻兘鎻忚堪:Precision Low Noise JFET Operational Amplifiers |
| ISL28210FRTZ | 鍒堕€犲晢:INTERSIL 鍒堕€犲晢鍏ㄧū:Intersil Corporation 鍔熻兘鎻忚堪:Precision Low Noise JFET Operational Amplifiers |
| ISL28210SOICEVAL1Z | 鍔熻兘鎻忚堪:EVAL BOARD FOR ISL28210 8SOIC RoHS:鏄� 椤炲垾:绶ㄧ▼鍣�锛岄枊鐧�(f膩)绯荤当(t菕ng) >> 瑭曚及鏉� - 閬嬬畻鏀惧ぇ鍣� 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯欐簴鍖呰:1 绯诲垪:- |
| ISL28213 | 鍒堕€犲晢:INTERSIL 鍒堕€犲晢鍏ㄧū:Intersil Corporation 鍔熻兘鎻忚堪:Single, Dual, Quad General Purpose Micropower, RRIO Operational Amplifier |
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