20 FN6631.7 February 25, 2013 The resistor-ESD diode configuration enables a wide differential input voltage range" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� ISL28207FBZ-T13
寤犲晢锛� Intersil
鏂囦欢闋佹暩(sh霉)锛� 13/31闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC OPAMP PREC LN DUAL 8-SOIC
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Solutions for Industrial Control Applications
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 2,500
鏀惧ぇ鍣ㄩ鍨嬶細 閫氱敤
闆昏矾鏁�(sh霉)锛� 2
杞�(zhu菐n)鎻涢€熺巼锛� 0.32 V/µs
澧炵泭甯跺绌嶏細 1MHz
闆绘祦 - 杓稿叆鍋忓锛� 15pA
闆诲 - 杓稿叆鍋忕Щ锛� 5µV
闆绘祦 - 闆绘簮锛� 210µA
闆绘祦 - 杓稿嚭 / 閫氶亾锛� 40mA
闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� 4.5 V ~ 40 V锛�±2.25 V ~ 20 V
宸ヤ綔婧害锛� -40°C ~ 125°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 8-SOIC锛�0.154"锛�3.90mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 8-SOIC
鍖呰锛� 甯跺嵎 (TR)
ISL28107, ISL28207, ISL28407
20
FN6631.7
February 25, 2013
The resistor-ESD diode configuration enables a wide differential
input voltage range equal to the lesser of the Maximum Supply
maximum of 0.5V beyond the V+ and V- supply voltage. The
internal protection resistors eliminate the need for external input
current limiting resistors in unity gain connections and other
circuit applications where large voltages or high slew rate signals
are present. Although the amplifier is fully protected, high input
slew rates that exceed the amplifier slew rate (卤0.32V/s) may
cause output distortion.
Output Current Limiting
The output current is internally limited to approximately 卤40mA
at +25掳C and can withstand a short circuit to either rail as long
as the power dissipation limits are not exceeded. This applies to
only one amplifier at a time for the dual op-amp. Continuous
operation under these conditions may degrade long-term
reliability.
Output Phase Reversal
Output phase reversal is a change of polarity in the amplifier
transfer function when the input voltage exceeds the supply
voltage. The ISL28107, ISL28207 and ISL28407 are immune to
output phase reversal, even when the input voltage is 1V beyond
the supplies.
Unused Channels
If the application only requires one channel, the user must
configure the unused channels to prevent them from oscillating.
The unused channels can oscillate if the input and output pins
are floating. This results in higher than expected supply currents
and possible noise injection into the channel being used. The
proper way to prevent this oscillation is to short the output to the
inverting input and ground the positive input, as shown in
Figure 55.
Power Dissipation
It is possible to exceed the +150掳C maximum junction
temperatures under certain load and power supply conditions. It
is therefore important to calculate the maximum junction
temperature (TJMAX) for all applications to determine if power
supply voltages, load conditions, or package type need to be
modified to remain in the safe operating area. These parameters
are related using Equation 1:
where:
PDMAXTOTAL is the sum of the maximum power dissipation of
each amplifier in the package (PDMAX)
PDMAX for each amplifier can be calculated using Equation 2:
where:
TMAX = Maximum ambient temperature
JA = Thermal resistance of the package
PDMAX = Maximum power dissipation of one amplifier
VS = Total supply voltage
IqMAX = Maximum quiescent supply current of one amplifier
VOUTMAX = Maximum output voltage swing of the application
RL = Load resistance
ISL28107, ISL28207, ISL28407 SPICE Model
Figure 56 shows the SPICE model schematic, and Figure 57 shows
the net list for the ISL28107, ISL28207 and ISL28407 SPICE
model. The model is a simplified version of the actual device and
simulates important AC and DC parameters. AC parameters
incorporated into the model are: 1/f and flatband noise, Slew
Rate, CMRR, Gain and Phase. The DC parameters are VOS, IOS,
total supply current and output voltage swing. The model uses
typical parameters given in the 鈥淓lectrical Specifications鈥� table
beginning on page 6. AVOL is adjusted for 155dB with the
dominant pole at 0.01Hz. CMRR is set (145dB, fcm = 100Hz). The
input stage models the actual device to present an accurate AC
representation. The model is configured for ambient temperature
of +25掳C.
Figures 58 through 68 show the characterization vs simulation
results for the Noise Voltage, Closed Loop Gain vs Frequency,
Closed Loop Gain vs RL, Large Signal Step Response, Open Loop
Gain Phase and Simulated CMRR vs Frequency.
License Statement
The information in this SPICE model is protected under the
United States copyright laws. Intersil Corporation hereby grants
users of this macro-model hereto referred to as 鈥淟icensee鈥�, a
nonexclusive, nontransferable licence to use this model as long
as the Licensee abides by the terms of this agreement. Before
using this macro-model, the Licensee should read this license. If
the Licensee does not accept these terms, permission to use the
model is not granted.
The Licensee may not sell, loan, rent, or license the macro-model,
in whole, in part, or in modified form, to anyone outside the
Licensee鈥檚 company. The Licensee may modify the macro-model
to suit his/her specific applications, and the Licensee may make
copies of this macro-model for use within their company only.
This macro-model is provided 鈥淎S IS, WHERE IS, AND WITH NO
WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED,
INCLUDING BUY NOT LIMITED TO ANY IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.鈥�
In no event will Intersil be liable for special, collateral, incidental, or
consequential damages in connection with or arising out of the
use of this macro-model. Intersil reserves the right to make
changes to the product and the macro-model without prior notice.
FIGURE 55. PREVENTING OSCILLATIONS IN UNUSED CHANNELS
-
+
T
JMAX
T
MAX
JAxPDMAXTOTAL
+
=
(EQ. 1)
PD
MAX
V
S
I
qMAX
V
S
(
- V
OUTMAX )
V
OUTMAX
R
L
----------------------------
+
=
(EQ. 2)
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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鍙冩暩(sh霉)鎻忚堪
ISL28207FBZ-T7 鍔熻兘鎻忚堪:IC OPAMP PREC LN DUAL 8-SOIC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> Linear - Amplifiers - Instrumentation 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:75 绯诲垪:MicroAmplifier™ 鏀惧ぇ鍣ㄩ鍨�:閫氱敤 闆昏矾鏁�(sh霉):1 杓稿嚭椤炲瀷:婊挎摵骞� 杞�(zhu菐n)鎻涢€熺巼:0.03 V/µs 澧炵泭甯跺绌�:100kHz -3db甯跺:- 闆绘祦 - 杓稿叆鍋忓:1pA 闆诲 - 杓稿叆鍋忕Щ:60µV 闆绘祦 - 闆绘簮:20µA 闆绘祦 - 杓稿嚭 / 閫氶亾:5mA 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±):2.3 V ~ 5.5 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-SOIC锛�0.154"锛�3.90mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:8-SOIC 鍖呰:绠′欢
ISL28207FBZ-T7A 鍔熻兘鎻忚堪:IC OPAMP GP 1MHZ DUAL LN 8SOIC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> Linear - Amplifiers - Instrumentation 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:2,500 绯诲垪:- 鏀惧ぇ鍣ㄩ鍨�:閫氱敤 闆昏矾鏁�(sh霉):2 杓稿嚭椤炲瀷:婊挎摵骞� 杞�(zhu菐n)鎻涢€熺巼:350 V/µs 澧炵泭甯跺绌�:180MHz -3db甯跺:320MHz 闆绘祦 - 杓稿叆鍋忓:12.5µA 闆诲 - 杓稿叆鍋忕Щ:800µV 闆绘祦 - 闆绘簮:15mA 闆绘祦 - 杓稿嚭 / 閫氶亾:85mA 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±):2.5 V ~ 12.6 V锛�±1.25 V ~ 6.3 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-TSSOP锛�8-MSOP锛�0.118"锛�3.00mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:8-MSOP 鍖呰:甯跺嵎 (TR)
ISL28207FRTZ 鍔熻兘鎻忚堪:IC OPAMP PREC 1MHZ DUAL LN 8TDFN RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> Linear - Amplifiers - Instrumentation 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:2,500 绯诲垪:- 鏀惧ぇ鍣ㄩ鍨�:閫氱敤 闆昏矾鏁�(sh霉):2 杓稿嚭椤炲瀷:鎺ㄦ尳寮�锛屾豢鎿哄箙 杞�(zhu菐n)鎻涢€熺巼:2.1 V/µs 澧炵泭甯跺绌�:22MHz -3db甯跺:- 闆绘祦 - 杓稿叆鍋忓:1pA 闆诲 - 杓稿叆鍋忕Щ:70µV 闆绘祦 - 闆绘簮:420µA 闆绘祦 - 杓稿嚭 / 閫氶亾:68mA 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±):2.4 V ~ 5.5 V锛�±1.2 V ~ 2.75 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:10-TFSOP锛�10-MSOP锛�0.118"锛�3.00mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:10-µMAX 鍖呰:甯跺嵎 (TR)
ISL28207FRTZ-T13 鍔熻兘鎻忚堪:IC OPAMP PREC 1MHZ DUAL LN 8TDFN RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> Linear - Amplifiers - Instrumentation 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:75 绯诲垪:MicroAmplifier™ 鏀惧ぇ鍣ㄩ鍨�:閫氱敤 闆昏矾鏁�(sh霉):1 杓稿嚭椤炲瀷:婊挎摵骞� 杞�(zhu菐n)鎻涢€熺巼:0.03 V/µs 澧炵泭甯跺绌�:100kHz -3db甯跺:- 闆绘祦 - 杓稿叆鍋忓:1pA 闆诲 - 杓稿叆鍋忕Щ:60µV 闆绘祦 - 闆绘簮:20µA 闆绘祦 - 杓稿嚭 / 閫氶亾:5mA 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±):2.3 V ~ 5.5 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-SOIC锛�0.154"锛�3.90mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:8-SOIC 鍖呰:绠′欢
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