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| 型號： | ISL28176FBZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 9/19頁 |
| 文件大小： | 0K |
| 描述： | IC OPAMP RRIO SGL 120UA 8-SOIC |
| 標準包裝： | 97 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉換速率： | 0.13 V/µs |
| 增益帶寬積： | 400kHz |
| 電流 - 輸入偏壓： | 400pA |
| 電壓 - 輸入偏移： | 20µV |
| 電流 - 電源： | 55µA |
| 電流 - 輸出 / 通道： | 31mA |
| 電壓 - 電源，單路/雙路(±)： | 2.4 V ~ 5 V，±1.2 V ~ 2.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOIC |
| 包裝： | 管件 |
17
FN6301.4
June 23, 2009
Enable/Disable Feature
The ISL28276 (QSOP package only) offers two EN pins
(EN_A and EN_B) which disable the op amp when pulled up
to at least 2.0V. In the disabled state (output in a high
impedance state), the part consumes typically 4A. By
disabling the part, multiple parts can be connected together
as a MUX. The outputs are tied together in parallel and a
channel can be selected by the EN pins. The loading effects
of the feedback resistors of the disabled amplifier must be
considered when multiple amplifier outputs are connected
together. The EN pin also has an internal pull-down. If left
open, the EN pin will pull to the negative rail and the device
will be enabled by default.
Using Only One Channel
The ISL28276 and ISL28476 are dual and quad channel
op amps. If the application only requires one channel when
using the ISL28276 or less than 4 channels when using the
ISL28476, the user must configure the unused channel(s) to
prevent them from oscillating. The unused channel(s) will
oscillate if the input and output pins are floating. This will
result in higher than expected supply currents and possible
noise injection into the channel being used. The proper way
to prevent this oscillation is to short the output to the
negative input and ground the positive input (as shown in
Figure 59).
Proper Layout Maximizes Performance
To achieve the maximum performance of the high input
impedance and low offset voltage, care should be taken in
the circuit board layout. The PC board surface must remain
clean and free of moisture to avoid leakage currents
between adjacent traces. Surface coating of the circuit board
will reduce surface moisture and provide a humidity barrier,
reducing parasitic resistance on the board. When input
leakage current is a concern, the use of guard rings around
the amplifier inputs will further reduce leakage currents.
Figure 60 shows a guard ring example for a unity gain
amplifier that uses the low impedance amplifier output at the
same voltage as the high impedance input to eliminate
surface leakage. The guard ring does not need to be a
specific width, but it should form a continuous loop around
both inputs. For further reduction of leakage currents,
components can be mounted to the PC board using Teflon
standoff insulators.
Current Limiting
The ISL28176, ISL28276 and ISL28476 have no internal
current-limiting circuitry. If the output is shorted, it is possible
to exceed the Absolute Maximum Rating for output current
or power dissipation, potentially resulting in the destruction
of the device.
Power Dissipation
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power-supply
conditions. It is therefore important to calculate the
maximum junction temperature (TJMAX) for all applications
to determine if power supply voltages, load conditions, or
package type need to be modified to remain in the safe
operating area. These parameters are related as follows:
where:
PDMAXTOTAL is the sum of the maximum power
dissipation of each amplifier in the package (PDMAX)
PDMAX for each amplifier can be calculated as follows:
where:
TMAX = Maximum ambient temperature
θ
JA = Thermal resistance of the package
PDMAX = Maximum power dissipation of 1 amplifier
VS = Supply voltage (Magnitude of V+ and V-)
IMAX = Maximum supply current of 1 amplifier
VOUTMAX = Maximum output voltage swing of the
application
RL = Load resistance
FIGURE 59. PREVENTING OSCILLATIONS IN UNUSED
CHANNELS
-
+
1/2 ISL28276
1/4 ISL28476
IN
V+
FIGURE 60. GUARD RING EXAMPLE FOR UNITY GAIN
AMPLIFIER
HIGH IMPEDANCE INPUT
T
JMAX
T
MAX
θ
JAxPDMAXTOTAL
()
+
=
(EQ. 1)
PD
MAX
2*V
S
I
SMAX
V
S
(
- V
OUTMAX )
V
OUTMAX
R
L
----------------------------
×
+
×
=
(EQ. 2)
ISL28176, ISL28276, ISL28476
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