14 FN6633.6 December 16, 2010 Applications Information Functional Description The ISL28127 and ISL28227 are single and dual," />
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鍨嬭櫉锛� ISL28127FBZ-T7
寤犲晢锛� Intersil
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鐢㈠搧鍩硅〒妯″锛� High Voltage Precision Operational Amplifiers
Solutions for Industrial Control Applications
妯欐簴鍖呰锛� 1,000
鏀惧ぇ鍣ㄩ鍨嬶細 閫氱敤
闆昏矾鏁革細 1
杞夋彌閫熺巼锛� 3.6 V/µs
澧炵泭甯跺绌嶏細 10MHz
闆绘祦 - 杓稿叆鍋忓锛� 1nA
闆诲 - 杓稿叆鍋忕Щ锛� 10µV
闆绘祦 - 闆绘簮锛� 2.2mA
闆绘祦 - 杓稿嚭 / 閫氶亾锛� 45mA
闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� 4.5 V ~ 40 V锛�±2.25 V ~ 20 V
宸ヤ綔婧害锛� -40°C ~ 125°C
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灏佽/澶栨锛� 8-SOIC锛�0.154"锛�3.90mm 瀵級
渚涙噳鍟嗚ō鍌欏皝瑁濓細 8-SOIC
鍖呰锛� 甯跺嵎 (TR)
ISL28127, ISL28227
14
FN6633.6
December 16, 2010
Applications Information
Functional Description
The ISL28127 and ISL28227 are single and dual, low noise
10MHz BW precision op amps. Both devices are fabricated in a
new precision 40V complementary bipolar DI process. A super-
beta NPN input stage with input bias current cancellation
provides low input bias current (1nA typical), low input offset
voltage (10V typ), low input noise voltage (3nV/
鈭欻z), and low
1/f noise corner frequency (5Hz). These amplifiers also feature
high open loop gain (1500V/mV) for excellent CMRR (120dB)
and THD+N performance (0.0002% @ 3.5VRMS, 1kHz into 2k惟).
A complimentary bipolar output stage enables high capacitive
load drive without external compensation.
Operating Voltage Range
The devices are designed to operate over the 4.5V (卤2.25V) to
40V (卤20V) range and are fully characterized at 10V (卤5V) and
30V (卤15V). Parameter variation with operating voltage is shown
in the 鈥淭ypical Performance Curves鈥� beginning on page 8.
Input ESD Diode Protection
The input terminals (IN+ and IN-) have internal ESD protection
diodes to the positive and negative supply rails, and an additional
anti-parallel diode pair across the inputs (see Figures 38 and 39).
For unity gain applications (see Figure 38) where the output is
connected directly to the non-inverting input a current limiting
resistor (RIN) will be needed under the following conditions to
protect the anti-parallel differential input protection diodes.
The amplifier input is supplied from a low impedance source.
The input voltage rate-of-rise (dV/dt) exceeds the maximum
slew rate of the amplifier (卤3.6V/s).
If the output lags far enough behind the input, the anti-parallel
input diodes can conduct. For example, if an input pulse ramps
from 0V to +10V in 1s, then the output of the ISL28x27 will reach
only +3.6V (slew rate = 3.6V/s) while the input is at 10V, The
input differential voltage of 6.4V will force input ESD diodes to
conduct, dumping the input current directly into the output stage
and the load. The resulting current flow can cause permanent
damage to the ESD diodes. The ESD diodes are rated to 20mA,
and in the previous example, setting RIN to 1k resistor (see Figure
38) would limit the current to < 6.4mA, and provide additional
protection up to 卤20V at the input.
In applications where one or both amplifier input terminals are at
risk of exposure to high voltage, current limiting resistors may be
needed at each input terminal (see Figure 39 RIN+, RIN-) to limit
current through the power supply ESD diodes to 20mA.
Output Current Limiting
The output current is internally limited to approximately 卤45mA
at +25掳C and can withstand an short circuit to either rail as long
as the power dissipation limits are not exceeded. This applies to
only 1 amplifier at a time for the dual op amp. Continuous
operation under these conditions may degrade long term
reliability.
Output Phase Reversal
Output phase reversal is a change of polarity in the amplifier
transfer function when the input voltage exceeds the supply
voltage. The ISL28127 and ISL28227 are immune to output
phase reversal, even when the input voltage is 1V beyond the
supplies.
Power Dissipation
It is possible to exceed the +150掳C maximum junction
temperatures under certain load and power supply conditions. It
is therefore important to calculate the maximum junction
temperature (TJMAX) for all applications to determine if power
supply voltages, load conditions, or package type need to be
modified to remain in the safe operating area. These parameters
are related using Equation 1:
where:
PDMAXTOTAL is the sum of the maximum power dissipation of
each amplifier in the package (PDMAX)
PDMAX for each amplifier can be calculated using Equation 2:
where:
TMAX = Maximum ambient temperature
胃JA = Thermal resistance of the package
PDMAX = Maximum power dissipation of 1 amplifier
VS = Total supply voltage
IqMAX = Maximum quiescent supply current of 1 amplifier
VOUTMAX = Maximum output voltage swing of the application
RL = Load resistance
FIGURE 38. INPUT ESD DIODE CURRENT LIMITING- UNITY GAIN
-
+
RIN
RL
VIN
VOUT
V+
V-
FIGURE 39. INPUT ESD DIODE CURRENT LIMITING -
DIFFERENTIAL INPUT
-
+
RIN-
RL
VIN-
VOUT
V+
V-
RIN+
VIN+
TJMAX
TMAX 胃JAxPDMAXTOTAL
+
=
(EQ. 1)
PDMAX
VS IqMAX VS
(
- VOUTMAX)
VOUTMAX
RL
------------------------
脳
+
脳
=
(EQ. 2)
鐩搁棞PDF璩囨枡
PDF鎻忚堪
S08B-XADSS-N CONN HDR XAD 8POS 2.5MM TIN SE
77317-104-62LF BERGSTIK
ISL28127FBZ-T13 IC OPAMP LN SGL 10MHZ 8-SOIC
961240-6700-AR-PR CONN HEADER STR DL 40PS GOLD SMD
180397-1 CONN RECPT FLAG 13-17AWG 0.250
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