24 FN6935.5 March 4, 2014 Submit Document Feedback *ISL28108_208 Macromodel - covers following *products *I" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� ISL28108FBZ-T13
寤犲晢锛� Intersil
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 17/34闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC OPAMP GP RR 1.2MHZ 8SOIC
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 2,500
鏀惧ぇ鍣ㄩ鍨嬶細 閫氱敤
闆昏矾鏁�(sh霉)锛� 1
杓稿嚭椤炲瀷锛� 婊挎摵骞�
杞�(zhu菐n)鎻涢€熺巼锛� 0.45 V/µs
澧炵泭甯跺绌嶏細 1.2MHz
闆绘祦 - 杓稿叆鍋忓锛� 13nA
闆诲 - 杓稿叆鍋忕Щ锛� 25µV
闆绘祦 - 闆绘簮锛� 185µA
闆绘祦 - 杓稿嚭 / 閫氶亾锛� 30mA
闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� 3 V ~ 40 V锛�±1.5 V ~ 20 V
宸ヤ綔婧害锛� -40°C ~ 125°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 8-SOIC锛�0.154"锛�3.90mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 8-SOIC
鍖呰锛� 甯跺嵎 (TR)
ISL28108, ISL28208, ISL28408
FN6935.5
March 4, 2014
*ISL28108_208 Macromodel - covers following
*products
*ISL28108
*ISL28208
*ISL28408
*
*Revision History:
* Revision B, LaFontaine January 22 2014
* Model for Noise, supply currents, CMRR
*128dB f=6kHz ,AVOL 122dB f=1Hz
* SR = 0.45V/us, GBWP 1.2MHz.
*Copyright 2011 by Intersil Corporation
*Refer to data sheet "LICENSE STATEMENT"
*Use of this model indicates your acceptance
*with the terms and provisions in the License
*Statement.
*
*Intended use:
*This Pspice Macromodel is intended to give
*typical DC and AC performance characteristics
*under a wide range of external circuit
*configurations using compatible simulation
*platforms 鈥� such as iSim PE.
*
*Device performance features supported by this
*model
*Typical, room temp., nominal power supply
*voltages used to produce the following
*characteristics:
*Open and closed loop I/O impedances,
*Open loop gain and phase,
*Closed loop bandwidth and frequency
*response,
*Loading effects on closed loop frequency
*response,
*Input noise terms including 1/f effects,
*Slew rate,
*Input and Output Headroom limits to I/O
*voltage swing,
*Supply current at nominal specified supply
*voltages.
*
*Device performance features NOT supported
*by this model:
*Harmonic distortion effects,
*Output current limiting (current will limit at
*40mA),
*Disable operation (if any),
*Thermal effects and/or over temperature
*parameter variation,
*Limited performance variation vs. supply
*voltage is modeled,
*Part to part performance variation due to
*normal process parameter spread,
*Any performance difference arising from
*different packaging source,
*Load current reflected into the power supply
*current.
*
* Connections:
+input
*
|
-input
*
|
+Vsupply
*
|
-Vsupply
*
|
output
*
|
.subckt ISL28108_208 Vin+ Vin-V+ V- VOUT
* source ISL28118_218_subckt_check_0
*
*Voltage Noise
E_En
VIN+ 6 2 0 0.3
D_D13
1 2 DN
D_D14
1 2 DN
V_V7
1 0 0.1
R_R17
2 0 1150
*
*Input Stage
Q_Q6
11 10 9 PNP_input
Q_Q7
8 7 9 PNP_input
Q_Q8
V-- VIN- 7 PNP_LATERAL
Q_Q9
V-- 12 10 PNP_LATERAL
I_I1
V++ 9 DC 12e-6
I_I2
V++ 7 DC 6E-6
I_I3
V++ 10 DC 6E-6
I_IOS
6 VIN- DC 3e-9
D_D1
7 10 DBREAK
D_D2
10 7 DBREAK
R_R1
5 6 5e11
R_R2
VIN- 5 5e11
R_R3
V-- 8 6250
R_R4
V-- 11 6250
C_Cin1
V-- VIN- 4.19e-12
C_Cin2
V-- 6 4.19e-12
C_CinDif
6 VIN- 1.21E-12
*
*1st Gain Stage
G_G1
V++ 14 8 11 0.4779867
G_G2
V-- 14 8 11 0.4779867
V_V1
13 14 -6.74
V_V2
14 15 -6.76
D_D3
13 V++ DX
D_D4
V-- 15 DX
R_R5
14 V++ 1
R_R6
V-- 14 1
*
*2nd Gain Stage
G_G3
V++ VG 14 VMID 261.748e-6
G_G4
V-- VG 14 VMID 261.748e-6
V_V3
16 VG -6.74
V_V4
VG 17 -6.76
D_D5
16 V++ DX
D_D6
V-- 17 DX
R_R7
VG V++ 7.62283e9
R_R8
V-- VG 7.62283e9
C_C1
VG V++ 2.31e-11
C_C2
V-- VG 2.31e-11
*
*Mid supply Ref
E_E2
V++ 0 V+ 0 1
E_E3
V-- 0 V- 0 1
E_E4
VMID V-- V++ V-- 0.5
I_ISY
V+ V- DC 185E-6
*
*Common Mode Gain Stage with Zero
G_G5
V++ 19 5 VMID 0.6
G_G6
V-- 19 5 VMID 0.6
G_G7
V++ VC 19 VMID 0.6
G_G8
V-- VC 19 VMID 0.6
E_EOS
12 6 VC VMID 1
L_L1
18 V++ 1.59159E-08
L_L2
20 V-- 1.59159E-08
L_L3
21 V++ 1.59159E-08
L_L4
22 V-- 1.59159E-08
R_R9
19 18 1e-3
R_R10
20 19 1e-3
R_R11
VC 21 1e-3
R_R12
22 VC 1e-3
*
*Pole Stage
G_G15
V++ 28 VG VMID 314.15e-6
G_G16
V-- 28 VG VMID 314.15e-6
R_R19
28 V++ 3.18319e3
R_R20
V-- 28 3.18319e3
C_C5
28 V++ 10e-12
C_C6
V-- 28 10e-12
*
G_G9
V++ 23 28 VMID 314.15e-6
G_G10
V-- 23 28 VMID 314.15e-6
R_R13
23 V++ 3.18319e3
R_R14
V-- 23 3.18319e3
C_C3
23 V++ 10e-12
C_C4
V-- 23 10e-12
*
*Output Stage with Correction Current Sources
G_G11
26 V-- VOUT 23 12.5e-3
G_G12
27 V-- 23 VOUT 12.5e-3
G_G13
VOUT V++ V++ 23 12.5e-3
G_G14
V-- VOUT 23 V-- 12.5e-3
D_D7
23 24 DX
D_D8
25 23 DX
D_D9
V-- 26 DY
D_D10
V++ 26 DX
D_D11
V++ 27 DX
D_D12
V-- 27 DY
V_V5
24 VOUT -0.4
V_V6
VOUT 25 -0.4
R_R15
VOUT V++ 80
R_R16
V-- VOUT 80
.model PNP_LATERAL pnp(is=1e-016 bf=250
va=80
+ ik=0.138 rb=0.01 re=0.101 rc=180 kf=0 af=1)
.model PNP_input pnp(is=1e-016 bf=100
va=80
+ ik=0.138 rb=0.01 re=0.101 rc=180 kf=0 af=1)
.model DBREAK D(bv=43 rs=1)
.model DN D(KF=6.69e-9 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends ISL28108_208
FIGURE 68. SPICE NET LIST
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
180464-1 CONN RCPT FLAG 17-13.5AWG .250
1SMC60AT3G TVS 1500W 60V UNIDIRECT SMC
1SMC6.5AT3G TVS 1500W 6.5V UNIDIRECT SMC
108458048001025 CONN HEADER MALE 48POS R/A
155208-5202-RB CONN HEADER 2MM 8POS R/A .112"
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鍙冩暩(sh霉)鎻忚堪
ISL28108FBZ-T7 鍔熻兘鎻忚堪:鏀惧ぇ鍣� IC 闁嬬櫦(f膩)宸ュ叿 ISL28108FBZ 40V LW PWR R-R OUT SNGL SUP RoHS:鍚� 鍒堕€犲晢:International Rectifier 鐢�(ch菐n)鍝�:Demonstration Boards 椤炲瀷:Power Amplifiers 宸ュ叿鐢ㄤ簬瑭�(p铆ng)浼�:IR4302 宸ヤ綔闆绘簮闆诲:13 V to 23 V
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ISL28108FRTZ 鍔熻兘鎻忚堪:鏀惧ぇ鍣� IC 闁嬬櫦(f膩)宸ュ叿 ISL28108FRTZ 40V LW PWR R-R OUT SNGL SUP RoHS:鍚� 鍒堕€犲晢:International Rectifier 鐢�(ch菐n)鍝�:Demonstration Boards 椤炲瀷:Power Amplifiers 宸ュ叿鐢ㄤ簬瑭�(p铆ng)浼�:IR4302 宸ヤ綔闆绘簮闆诲:13 V to 23 V
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ISL28108FRTZ-T7 鍔熻兘鎻忚堪:鏀惧ぇ鍣� IC 闁嬬櫦(f膩)宸ュ叿 ISL28108FRTZ 40V LW PWR R-R OUT SNGL SUP RoHS:鍚� 鍒堕€犲晢:International Rectifier 鐢�(ch菐n)鍝�:Demonstration Boards 椤炲瀷:Power Amplifiers 宸ュ叿鐢ㄤ簬瑭�(p铆ng)浼�:IR4302 宸ヤ綔闆绘簮闆诲:13 V to 23 V
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