5 FN7585.0 February 23, 2011 VOH Output Swing High I
參數(shù)資料
型號: ISL24211IRTZ
廠商: Intersil
文件頁數(shù): 8/12頁
文件大?。?/td> 0K
描述: IC VCOM CALIBRATOR I2C 10TDFN
標(biāo)準(zhǔn)包裝: 100
類型: 校準(zhǔn)器
應(yīng)用: LCD 驅(qū)動器,基準(zhǔn)電壓發(fā)生器
安裝類型: 表面貼裝
封裝/外殼: 10-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 10-TDFN(3x3)
包裝: 管件
ISL24211
5
FN7585.0
February 23, 2011
VOH
Output Swing High
IL = 5mA
17.85
17.9
V
ISC
Short Circuit Current (Sinking)
300
430
mA
Short Circuit Current (Sourcing)
450
555
mA
SR
Slew Rate (Rising)
1k
Ω || 8pF Load
70
116
V/s
Slew Rate (Falling)
1k
Ω || 8pF Load
50
93
V/s
tS
Settling Time to 0.2%
150
ns
BW
-3dB Bandwidth
60
MHz
I2C INPUTS AND OUTPUT
VIH_I2C
SDA, SCL Logic 1 Input Voltage
1.44
V
VIL_I2C
SDA, SCL Logic 0 Input Voltage
0.55
V
VHYS_I2C SDA, SCL Hysteresis
260
mV
IL_I2C
SDA, SCL Input Leakage Current
±1
A
VOL_I2C
SDA Output Logic Low
I = -3mA
0.4
V
VIH_WP
WP Input Logic High
0.7VDD
V
VIL_WP
WP Input Logic Low
0.3VDD
V
VHYS_WP WP Input Hysteresis
260
mV
IL_WP
WP Input Leakage Current
-0.20
-0.5
-1
A
I2C TIMING
fCLK
I2C Clock Frequency
400
kHz
tSCH
I2C Clock High Time
0.6
s
tSCL
I2C Clock Low Time
1.3
s
tDSP
I2C Spike Rejection Filter Pulse Width
050
ns
tSDS
I2C Data Set Up Time
250
ns
tSDH
I2C Data Hold Time
250
ns
tBUF
I2C Time Between Stop and Start
200
s
tSTS
I2C Repeated Start Condition Set-up
0.6
s
tSTH
I2C Repeated Start Condition Hold
0.6
s
tSPS
I2C Stop Condition Set-up
0.6
s
CSDA
SDA Pin Capacitance
10
pF
CSCL
SCL Pin Capacitance
10
pF
tWR
EEPROM Write Cycle Time
100
ms
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Electrical Specifications Test Conditions: VDD = 3.3V, AVDD = 18V, RSET = 5kΩ, R1 = 10kΩ, R2 = 10kΩ, (See Figure 5), VCOM_OUT pin
connected to INN, unless otherwise specified. Typicals are at TA = +25°C. Boldface limits apply over the operating temperature range,
-40°C to +85°C.
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
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