5 FN7586.1 December 9, 2010 Application Information The ISL24201 provides the ability to adjust the V
參數(shù)資料
型號: ISL24201IRTZ
廠商: Intersil
文件頁數(shù): 8/12頁
文件大?。?/td> 0K
描述: IC VCOM CALIBRATOR I2C 8TDFN
標準包裝: 100
類型: 校準器
應(yīng)用: LCD 顯示器
安裝類型: 表面貼裝
封裝/外殼: 8-WSDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 8-TDFN(3x3)
包裝: 管件
ISL24201
5
FN7586.1
December 9, 2010
Application Information
The ISL24201 provides the ability to adjust the VCOM voltage
during production test and alignment, under digital control, to
minimize the flicker of an LCD panel. A digitally controlled
potentiometer (DCP), with 256 steps of resolution, adjusts the sink
current of the OUT pin. Figure 3 shows the VCOM adjustment using
a mechanical potentiometer circuit and the equivalent circuit
replacement with the ISL24201.
The output is connected to an external voltage divider, as shown in
Figure 3, so that the ISL24201 will have the ability to reduce the
voltage on the output by increasing the OUT pin sink current. The
amount of current sunk is controlled by the I2C serial interface.
I2C TIMING
fCLK
I2C Clock Frequency
400
kHz
tSCH
I2C Clock High Time
0.6
s
tSCL
I2C Clock Low Time
1.3
s
tDSP
I2C Spike Rejection Filter Pulse Width
050
ns
tSDS
I2C Data Set Up Time
250
ns
tSDH
I2C Data Hold Time
250
ns
tBUF
I2C Time Between Stop and Start
200
s
tSTS
I2C Repeated Start Condition Set-up
0.6
s
tSTH
I2C Repeated Start Condition Hold
0.6
s
tSPS
I2C Stop Condition Set-up
0.6
s
CSDA
SDA Pin Capacitance
10
pF
CS
SCL Pin Capacitance
10
pF
tW
EEPROM Write Cycle Time
100
ms
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Electrical Specifications Test Conditions: VDD = 3.3V, AVDD = 18V, RSET= 5kΩ, R1 = 10kΩ, R2 = 10kΩ, (See Figure 5); unless otherwise
specified. Typicals are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
OUT
SET
ISL24201
or
ISL24202
R1
R2
AVDD
VCOM
IOUT
VDD
RSET
RA
RC
AVDD
VCOM
RB
R1 = RA
R2 = RB+RC
RSET = RARB + RARC
20RB
FIGURE 3. MECHANICAL ADJUSTMENT REPLACEMENT
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