11 FN6637.1 October 18, 2011 Printed Circuit Board Layout As with any high-frequency device, good printed circuit board layout is nece" />
參數(shù)資料
型號: ISL24021IRT065Z-T7A
廠商: Intersil
文件頁數(shù): 3/13頁
文件大?。?/td> 0K
描述: IC OPAMP RRIO 1A 25MHZ 8-TDFN
標(biāo)準(zhǔn)包裝: 1
放大器類型: 電壓反饋
電路數(shù): 1
輸出類型: 滿擺幅
轉(zhuǎn)換速率: 19 V/µs
-3db帶寬: 27MHz
電流 - 輸入偏壓: 2nA
電壓 - 輸入偏移: 1400µV
電流 - 電源: 2.2mA
電流 - 輸出 / 通道: 300mA
電壓 - 電源,單路/雙路(±): 4.5 V ~ 19 V,±2.25 V ~ 9.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-WDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 8-TDFN(3x3)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: ISL24021IRT065Z-T7ADKR
ISL24021
11
FN6637.1
October 18, 2011
Printed Circuit Board Layout
As with any high-frequency device, good printed circuit board
layout is necessary for optimum performance. For the ISL24021
low impedance analog power and ground planes are
recommended, and trace lengths should be as short as possible.
The power supply pins must be well bypassed to reduce the risk
of oscillation. For optimal thermal and operating performance
the ISL24021 thermal pad should always be connected to the
lowest potential, VSS.
For normal single supply operation (the VSS pin is connected to
GND) a 4.7F capacitor should be placed from VDD to GND, then
a parallel 0.1F capacitor should be connected as close to the
amplifier as possible. For dual supply operation the same
bypassing techniques should be utilized by connecting capacitors
from each supply to GND.
FIGURE 28. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY (4-LAYER) TEST BOARD - TDFN
EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5
0
0.5
1.0
1.5
2.0
2.5
3.0
0
25
50
75
100
125
150
AMBIENT TEMP (°C)
POWE
R
DI
SSI
P
A
TI
ON
(W)
θJA = +50 (°C/W)
2.5W
TDFN8
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