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ISL23445
9
FN7874.0
June 21, 2011
DCP Macro Model
Timing Diagrams
32pF
RH
RTOTAL
CH
32pF
CW
CL
32pF
RW
RL
Input Timing
Output Timing
XDCP Timing (For All Load Instructions)
...
CS
SCK
SDI
SDO
MSB
LSB
tLEAD
tH
tSU
tFI
tCS
tLAG
tCYC
tWL
...
tRI
tWH
...
CS
SCK
SDO
SDI
ADDR
MSB
LSB
tDIS
tHO
tV
...
tSO
...
CS
SCK
SDI
MSB
LSB
VW
tDCP
...
SDO
*When CS is HIGH
SDO at Z or Hi-Z state