
ISL23348
2
FN7903.1
August 24, 2011
Block Diagram
POWER UP
INTERFACE
CONTROL
AND
STATUS
LOGIC
I/O
BLOCK
GND
SCL
SDA
A0
A1
A2
VLOGIC
LEVEL
SHIFTER
WR0
VOLATILE
REGISTER
WR1
VOLATILE
REGISTER
WR2
VOLATILE
REGISTER
WR3
VOLATILE
REGISTER
RH0
RW0
RL0
RH1
RW1
RL1
RH2
RW2
RL2
RH3
RW3
RL3
VCC
Pin Configurations
ISL23348
(20 LD TSSOP)
TOP VIEW
ISL23348
(20 LD QFN)
TOP VIEW
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
RL0
RW0
VCC
RH0
RL1
RW1
GND
RH1
VLOGIC
A0
RL3
RH3
RL2
RW2
RW3
RH2
SCL
SDA
A2
A1
V
LO
GIC
RW1
SCL
RH2
A0
A1
RL0
RW
0
RL3
A2
RL2
RH0
RW2
RW
3
VCC
RL1
RH1
SDA
1
2
3
4
5
78
9
10
15
14
13
12
11
20
19
18
17
6
GND
6
RH3
16
Pin Descriptions
TSSOP
QFN
SYMBOL
DESCRIPTION
1
19
RL0
DCP0 “l(fā)ow” terminal
220
RW0
DCP0 wiper terminal
31
VCC
Analog power supply.
Range 1.7V to 5.5V
4
2
RH0
DCP0 “high” terminal
5
3
RL1
DCP1 “l(fā)ow” terminal
64
RW1
DCP1 wiper terminal
7
5
RH1
DCP1 “high” terminal
8
6
GND
Ground pin
97
VLOGIC I2C bus /logic supply. Range 1.2V to 5.5V
10
8
A0
Logic Pin - Hardwire slave address pin for
I2C serial bus.
Range: VLOGIC or GND
11
9
A1
Logic Pin - Hardwire slave address pin for
I2C serial bus.
Range: VLOGIC or GND
12
10
A2
Logic Pin - Hardwire slave address pin for
I2C serial bus.
Range: VLOGIC or GND
13
11
SDA
Logic Pin - Serial bus data input/open
drain output
14
12
SCL
Logic Pin - Serial bus clock input
15
13
RH2
DCP2 “high” terminal
16
14
RW2
DCP2 wiper terminal
17
15
RL2
DCP2 “l(fā)ow” terminal
18
16
RH3
DCP3 “high” terminal
19
17
RW3
DCP3 wiper terminal
20
18
RL3
DCP3 “l(fā)ow” terminal